Stackable Multi-Chip Package With Offset Face-to-Face Configuration

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Solution Overview

Problem

The electronic industry faces challenges in creating smaller, more reliable, and cost-effective integrated circuit packages that provide improved thermal performance, structural integrity, and electromagnetic interference (EMI) mitigation, while managing heat dissipation and warpage issues in stackable multi-chip packages.

Innovation Solution

A stackable multi-chip package system is designed with staggered dual land rows and an offset face-to-face configuration of integrated circuit dice, incorporating external interconnects with through holes and an encapsulation that includes a paddle for thermal dissipation and structural support, along with mold interlock features for enhanced rigidity and EMI shielding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If package stacks are made by stacking packages that have already passed the necessary tests, then the yields and reliability of these package stacks are higher, but the package stacks are thicker

Engineering Contradiction:
Improveyield and reliabilityVSAvoidpackage thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The package is divided into multiple subassemblies, each containing an integrated circuit die and external interconnect. These subassemblies are stacked and molded together to form a complete package, allowing individual testing at the subassembly level while achieving a thinner overall package structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from horizontal stacking of complete packages to vertical stacking of package subassemblies with offset face-to-face configuration. This dimensional reorganization allows for interlocking molding that reduces overall package thickness while maintaining structural integrity and reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If stacking features are added to provide structural and electrical integrity, then the structural and electrical uniformity is improved, but the manufacturing becomes difficult to control with incompatible materials

Engineering Contradiction:
Improvestructural and electrical integrityVSAvoidmanufacturing control
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The external interconnect is designed to serve multiple functions simultaneously: providing structural support, establishing electrical connections, and enabling mechanical interlocking between stacked subassemblies. This multi-functionality eliminates the need for separate stacking features and their associated material compatibility issues

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the stacking feature functionality into the external interconnect structure itself. The staggered dual land row configuration of the external interconnect provides both electrical connection and mechanical stacking alignment, simplifying manufacturing by reducing the number of separate components and material types

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If more circuitry is packed into the integrated circuits, then the functionality is increased, but more heat is generated degrading the performance and reliability

Engineering Contradiction:
ImprovefunctionalityVSAvoidheat generation
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The invention moves from two-dimensional heat dissipation to three-dimensional thermal management by stacking multiple subassemblies vertically. This allows heat to be distributed across multiple external interconnects and dissipated through multiple surfaces, improving thermal performance while maintaining high functionality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The package is segmented into multiple subassemblies, each generating heat that can be independently managed. The external interconnect structure provides multiple thermal pathways for heat dissipation, preventing heat accumulation and maintaining reliability in high-functionality configurations

Inventive Principle:
Principle #1Segmentation

4Length of stationary object

If the package height is reduced to achieve smaller form factor, then the size is decreased, but the structural integrity and warpage control become more difficult

Engineering Contradiction:
Improvepackage heightVSAvoidstructural integrity
Core Design Contradiction:
Length of stationary objectVSStrength

Solution Approach 1:

The invention uses asymmetric offset face-to-face configuration of the stacked subassemblies. This asymmetric arrangement creates interlocking geometry that enhances structural rigidity and prevents warpage, allowing for reduced package height without compromising strength

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The external interconnects are designed with predetermined staggered configurations that pre-establish mechanical interlocking and alignment features. This preliminary structural design ensures warpage control and structural integrity are built into the package architecture before final assembly, enabling thinner profiles

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8432026B2Stackable multi-chip package system
Publication Date: 2013.04.30 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8432026B2 patent drawing
  • US8432026B2 patent drawing
  • US8432026B2 patent drawing

AI summary

A stackable multi-chip package system is provided including forming a first external interconnect having a first through hole and a second external interconnect having a second through hole, forming a first package subassembly having the first external interconnect and a first integrated circuit die, forming a second package subassembly having the second external interconnect and a second integrated circuit die, mounting the second package subassembly over the first package subassembly, and molding the first package subassembly and the second package subassembly.