Stackable IC Die Mounting System with Vertical Bus Interconnect
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Solution Overview
Problem
Incorporating a large number of integrated circuits (ICs) into smaller electronic devices poses challenges such as electrically interconnecting ICs in tight spaces, managing thermal expansion, and ensuring reliable connections, while larger ICs have reduced yields and increased costs due to manufacturing limitations.
Innovation Solution
A stackable die mounting system with a base chip carrier that interfaces with a circuit board and stacked IC chip carriers, using a vertical bus configuration with solder columns to eliminate horizontal cabling and enable efficient, space-saving interconnects between ICs, allowing for additional processing power and memory without increasing circuit board area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple ICs are stacked horizontally or in parallel configuration with individual ribbon cables, then electrical interconnection between ICs is achieved, but assembly complexity increases and space efficiency decreases
Solution Approach 1:
The patent combines multiple individual ribbon cables into a single integrated cable assembly that simultaneously connects multiple ICs in a stack. This merging approach reduces the number of separate connection operations required during assembly, directly addressing the contradiction by simplifying the assembly process while maintaining electrical interconnection functionality.
Solution Approach 2:
The patent transitions from horizontal or parallel IC stacking to a vertical stack configuration. This dimensional change allows multiple ICs to be interconnected through a single cable assembly that routes vertically through the stack, reducing assembly complexity compared to horizontal configurations that require multiple separate cable loops.
2Adaptability or versatility
If larger ICs are used to provide more functions, then functionality increases, but manufacturing yield decreases and cost increases
Solution Approach 1:
The patent divides the functional requirements into multiple smaller ICs stacked vertically, with each IC performing a subset of functions. This segmentation allows each individual IC to remain within manufacturing yield specifications while the stacked assembly collectively provides the full functionality, resolving the contradiction between functionality and manufacturing yield.
Solution Approach 2:
The patent implements a nested structure where multiple functional ICs are stacked within a single vertical space. This nesting approach enables the system to achieve high functionality equivalent to large ICs while using smaller, higher-yield components, thereby maintaining reliability while providing adaptability.
3Area of stationary object
If ICs are tightly packaged to reduce device size, then space efficiency improves, but thermal management and vibration resistance become more difficult
Solution Approach 1:
The patent arranges ICs in a vertical stack configuration rather than spreading them horizontally across the circuit board. This dimensional change achieves high space efficiency by utilizing the vertical dimension, while the vertical cable assembly provides natural flexibility to accommodate thermal expansion and vibration without transmitting excessive stress to the ICs.
Solution Approach 2:
The patent employs flexible ribbon cables in the vertical interconnection assembly. These flexible cables can accommodate thermal expansion and contraction of the ICs during operation, as well as absorb vibration effects, thereby protecting the rigid IC components from harmful mechanical stresses while maintaining tight packaging.
4Device complexity
If vertical stacking with single cable assembly is implemented, then assembly complexity reduces and space efficiency improves, but routing density requirements increase
Solution Approach 1:
The patent routes all electrical connections vertically through a single cable assembly, utilizing the vertical dimension for signal transmission. This approach consolidates routing into a single organized path, reducing the need for complex horizontal routing strategies and minimizing routing density requirements on the circuit board while simplifying assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for increased IC density in small devices with faster clock speeds and reduced assembly complexity, achieving efficient vertical interconnects that reduce costs and improve reliability by using functionally identical ICs and minimizing the need for complex routing strategies.
Implementation Method 1
interconnecting the stacked IC chip carriers to the base chip carrier and to one another with solder columns
Data Source
AI summary
A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.