Vertically Stackable Dies With Chip Identifier Structures

Solution Overview

Problem

Conventional vertically stacked memory dies face increased complexity and costs due to the need for programming, sorting, and separating each die, limiting usable memory density and requiring next-generation memory dies to meet memory density requirements.

Innovation Solution

A semiconductor device with a vertically stacked multi-die configuration where each die has a physically predetermined chip identifier structure and shares a channel interface, eliminating the need for programming or sorting, and using through silicon vias (TSVs) to communicate chip identifiers and data, allowing for simpler logistics and reduced costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional vertically stacked memory dies are used, then memory density can be increased, but stacking complexity and costs increase due to programming, sorting, and separating each die

Engineering Contradiction:

Improvememory densityVSAvoidstacking complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies homogeneity by making all memory dies in the vertical stack identical in structure and function. Each die has the same chip identifier structure with TSVs configured to provide unique identification through their physical arrangement rather than through programming or sorting. This eliminates the need for complex post-fabrication processing while maintaining high memory density through vertical stacking.

Inventive Principle:

Principle #33Homogeneity

Solution Approach 2:

The patent implements preliminary action by pre-configuring the chip identifier structures during die fabrication. The TSVs are physically arranged and connected in specific patterns that encode unique identifiers for each die position in the stack. This preliminary configuration eliminates the need for subsequent programming or sorting operations, reducing stacking complexity while enabling high-density vertical stacking.

Inventive Principle:

Principle #10Preliminary action

2Quantity of substance

If conventional vertically stacked memory dies are used, then memory density can be increased, but costs increase due to programming, sorting, marking, or separating each die

Engineering Contradiction:

Improvememory densityVSAvoidmanufacturing cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent applies homogeneity by making all memory dies in the vertical stack identical in structure and function. Each die has the same chip identifier structure with TSVs configured to provide unique identification through their physical arrangement rather than through programming or sorting. This eliminates the need for complex post-fabrication processing while maintaining high memory density through vertical stacking.

Inventive Principle:

Principle #33Homogeneity

Solution Approach 2:

The patent implements preliminary action by pre-configuring the chip identifier structures during die fabrication. The TSVs are physically arranged and connected in specific patterns that encode unique identifiers for each die position in the stack. This preliminary configuration eliminates the need for subsequent programming or sorting operations, reducing stacking complexity while enabling high-density vertical stacking.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If memory die size is limited to be less than logic die size for stacking, then stacking process throughput is maintained, but usable memory density is limited

Engineering Contradiction:

Improvestacking process throughputVSAvoidusable memory density

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies dimensionality change by transitioning from horizontal memory expansion to vertical stacking architecture. Multiple memory dies are stacked in the vertical dimension, with each die maintaining identical size to the logic die for optimal throughput. The chip identifier structures use TSVs extending through the vertical stack to provide unique identification, enabling high memory density without compromising stacking process throughput.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8698321B2Vertically stackable dies having chip identifier structures

Publication Date: 2014.04.15 QUALCOMM INC

AI summary

A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.