Vertically Stackable Dies With Chip Identifier Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional vertically stacked memory dies face increased complexity and costs due to the need for programming, sorting, and separating each die, limiting usable memory density and requiring next-generation memory dies.
Innovation Solution
A semiconductor device with a stack of multiple dies, where each die has a physically predetermined chip identifier structure and shares a channel interface, eliminating the need for programming or sorting, and using through vias to communicate chip identifiers and data, allowing for simpler logistics and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertically stacked memory dies are used to increase memory density, then memory density is improved, but stacking complexity and costs increase due to programming, sorting, and separating each die
Solution Approach 1:
The patent applies homogeneity by making all memory dies in the vertical stack identical in structure and function. Each die has the same chip identifier structure with through vias configured in the same pattern, eliminating the need for individual programming, sorting, or separation. This uniform approach allows high memory density through vertical stacking while avoiding the complexity and costs associated with conventional differentiated die approaches
2Quantity of substance
If conventional vertically stacked memory dies are used to meet memory density requirements, then memory density is improved, but costs increase due to programming, sorting, marking, or separating each die
Solution Approach 1:
The patent eliminates manufacturing costs associated with individual die processing by making all dies identical. The uniform chip identifier structure with through vias configured in the same pattern across all dies removes the need for programming, sorting, marking, or separating operations, thereby reducing manufacturing costs while achieving high memory density
Solution Approach 2:
The chip identifier structure uses physical characteristics (through via configurations) that are inherently different for each die position in the stack, allowing automatic identification without external programming or sorting. Each die's unique position in the vertical stack is self-evident through its physical structure, eliminating costly post-fabrication processing
3Productivity
If memory die size is limited to be less than logic die size for stacking, then stacking process throughput is improved, but usable memory density decreases
Solution Approach 1:
The patent enables memory dies to be made as large as logic dies by using identical structures with uniform chip identifier configurations. This removes the size limitation constraint, allowing maximum memory die area while maintaining stacking throughput, thereby maximizing usable memory density without compromising manufacturing efficiency
Data Source
AI summary
A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through vias that are each hard wired to an external electrical contact.