Stackable IC Package with Interposer Substrates
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Solution Overview
Problem
Current integrated circuit packages face challenges in achieving simplified manufacturing processing, smaller dimensions, lower costs, increased functionality, and higher IO connectivity while maintaining reliability and flexibility, which have not been adequately addressed by existing solutions.
Innovation Solution
The integration of a lower interposer substrate with partially exposed conductors, a die mounted over it, and an upper interposer substrate with partially exposed conductors, encapsulated by a stack encapsulant, providing enhanced connectivity and scalability in a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate integrated circuit packages are used to achieve high IO connectivity and complex functions, then functionality and connectivity are improved, but package count, footprint area, and manufacturing complexity increase
Solution Approach 1:
The patent implements a stacked package architecture where multiple integrated circuit packages are vertically arranged and interconnected through interposer substrates. The lower package contains a die mounted on a lower interposer substrate, while the upper package contains another die mounted on an upper interposer substrate. The upper package is positioned directly over the lower package, creating a vertical stack that integrates multiple functions and high IO connectivity within a compact footprint, effectively applying the nesting principle to three-dimensional space.
Solution Approach 2:
The patent transitions from a traditional two-dimensional lateral arrangement of multiple packages to a three-dimensional vertical stacking configuration. By utilizing the vertical dimension (Z-axis) rather than only horizontal expansion (X-Y plane), the system achieves high IO connectivity and complex functionality without increasing the footprint area, as the packages are stacked one above another and connected through vertical interconnects via interposer substrates.
2Adaptability or versatility
If traditional packaging methods are used, then manufacturing is simpler, but IO connectivity and functionality are limited
Solution Approach 1:
The patent introduces interposer substrates as intermediary components between the dice and the package substrates. The lower interposer substrate provides electrical interconnection between the lower die and the lower package substrate, while the upper interposer substrate similarly connects the upper die to the upper package substrate. These interposer substrates act as mediators that enable high-density vertical interconnects and facilitate the stacked architecture, allowing enhanced IO connectivity while managing the complexity through standardized intermediary components.
3Volume of moving object
If package size is reduced to meet small dimensional requirements, then compactness is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent divides the integrated circuit system into separate modular packages stacked vertically, with each package containing a die, interposer substrate, and package substrate as distinct segments. This segmentation allows each component to be manufactured and tested independently with standard precision requirements, then assembled through controlled vertical stacking. The interposer substrates serve as alignment references that facilitate precise registration between stacked packages, maintaining manufacturing precision while achieving compact volume through vertical integration rather than lateral miniaturization.
Data Source
AI summary
An integrated circuit package system includes: providing a lower interposer substrate with lower exposed conductors; attaching a die over the lower interposer substrate; applying a stack encapsulant over the die and the lower interposer substrate having the lower exposed conductors partially exposed adjacent the stack encapsulant; and attaching an upper interposer substrate having upper exposed conductors over the stack encapsulant and with the upper exposed conductors substantially exposed.