Stackable IC Package with Lead Frame Interconnects for Density and Yield

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Solution Overview

Problem

Current integrated circuit packaging technologies face challenges in reducing package dimensions, achieving low-cost manufacturing, and providing flexible stacking and integration configurations while ensuring known-good-die (KGD) quality and assembly process yields.

Innovation Solution

A stackable integrated circuit package system is developed, featuring a lead frame with external interconnects that include die-attach and non-die-attach lead tips, allowing for flexible stacking and integration, and using existing manufacturing equipment to reduce costs and increase yields.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional multi-chip modules are used to reduce board space, then integration density is improved, but assembly process yield deteriorates due to inability to test die before assembly

Engineering Contradiction:

Improveintegration densityVSAvoidassembly process yield

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by enabling die testing to be performed before assembly into the multi-chip module. Individual die are tested separately on test substrates, allowing known-good-die identification prior to final assembly, thus resolving the yield problem while maintaining integration density

Inventive Principle:

Principle #10Preliminary action

2Volume of moving object

If leaded packages are used for stacking, then package dimensions are reduced, but I/O flexibility deteriorates due to limited input and output capabilities

Engineering Contradiction:

Improvepackage dimensionsVSAvoidI/O flexibility

Core Design Contradiction:

Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent transitions from two-dimensional leaded package connections to three-dimensional interconnect structures. Multiple interconnect interfaces are stacked vertically, allowing high I/O counts and flexible configurations while maintaining compact package dimensions through vertical integration

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If existing manufacturing methods are reused to reduce cost, then manufacturing cost is reduced, but package dimension reduction capability deteriorates

Engineering Contradiction:

Improvemanufacturing costVSAvoidpackage dimension reduction

Core Design Contradiction:

Ease of manufactureVSVolume of moving object

Solution Approach 1:

The patent creates universal manufacturing processes that can produce both traditional two-dimensional packages and advanced three-dimensional stacked packages using the same equipment and methods. This multi-functionality allows cost reduction through existing manufacturing infrastructure while achieving package dimension reduction through vertical stacking capabilities

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8232658B2Stackable integrated circuit package system with multiple interconnect interface

Publication Date: 2012.07.31 STATS CHIPPAC LTD

AI summary

A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.