Stackable IC Package with Offset Die and Spacer Interconnect
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Solution Overview
Problem
Existing integrated circuit package technologies face challenges in reducing package dimensions, increasing manufacturing yield, and lowering costs while accommodating more integrated circuits in shrinking physical spaces, as they struggle with space requirements for electrical connections and spacers that increase manufacturing costs and limit height reduction.
Innovation Solution
A stackable integrated circuit package system is developed, featuring a first external interconnect, a first integrated circuit die mounted below it, and a second die stacked in an offset configuration, with the second die partially exposed and connected via bond wires or ribbon bond wires, using a spacer and stiffener for mechanical support and heat dissipation, and encapsulated with a recessed epoxy mold compound to reduce size and enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple integrated circuit dice are stacked using existing package technologies, then more functions are integrated, but package height and space requirements increase due to spacers and electrical connection structures
Solution Approach 1:
The patent merges the spacer structure with the electrical connection function by forming conductive traces directly on the spacer substrate, eliminating the need for separate spacer and interconnect structures. This integration reduces overall package height while maintaining both mechanical support and electrical connectivity functions.
Solution Approach 2:
The patent transitions from traditional lateral electrical connections to vertical connections through the stacked dice architecture, with conductive traces routed on the spacer substrate to enable inter-die connectivity in the vertical dimension, thereby reducing the horizontal footprint while maintaining connection functionality.
2Strength
If spacers and additional structures are used to support stacked integrated circuits, then mechanical support is provided, but manufacturing complexity and costs increase
Solution Approach 1:
The spacer substrate serves multiple functions simultaneously: it provides mechanical support between dice, acts as a carrier for conductive traces for electrical connections, and serves as a structural element for encapsulation. This multi-functionality reduces the number of separate components and manufacturing steps required.
Solution Approach 2:
The patent employs a composite structure where the spacer substrate integrates mechanical support properties with electrical conductivity through deposited trace patterns, combining structural and electrical functions in a single composite element that simplifies manufacturing.
3Quantity of substance
If traditional package technologies are used to accommodate more integrated circuits, then integration density increases, but package dimensions and space occupation increase
Solution Approach 1:
The patent arranges multiple integrated circuit dice in a vertical stack rather than a lateral array, transitioning from two-dimensional to three-dimensional packaging. This vertical stacking dramatically reduces the horizontal footprint while accommodating multiple dice, achieving high integration density without increasing package area.
4Reliability
If wire loops and bond wires are used for electrical connections in stacked packages, then connectivity is achieved, but space requirements and manufacturing complexity increase
Solution Approach 1:
The patent extracts the electrical connection function from traditional bulky wire loops and bond wires, replacing them with planar conductive traces deposited directly on the spacer substrate. This extraction eliminates the need for three-dimensional wire routing, reducing space requirements while maintaining electrical connectivity.
Data Source
AI summary
A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.