Stackable IC Package with Through-Silicon Vias for Reduced Z-Height

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Solution Overview

Problem

Current integrated circuit packaging systems face challenges in reducing size while maintaining performance and reliability, with a need for simplified manufacturing, reduced electrical components on circuit boards, and increased functionality, which prior solutions have failed to adequately address.

Innovation Solution

The method involves a package base with a silicon interposer having through silicon vias connected to a device, encapsulated with a protrusion on the outward base side, allowing for multiple component stacking and reduced package size, while maintaining connectivity and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple electrical parts are mounted on circuit boards to achieve increased functionality, then product features and performance are improved, but product size and complexity increase

Engineering Contradiction:
ImprovefunctionalityVSAvoidproduct size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements package-on-package stacking where multiple integrated circuit packages are vertically stacked and interconnected through through-silicon vias (TSVs). This nesting approach allows multiple functional components to be integrated in the vertical dimension rather than spreading them horizontally, thereby increasing functionality while reducing the footprint area on circuit boards.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The invention transitions from a two-dimensional layout of electrical parts on circuit boards to a three-dimensional stacked architecture. By utilizing the vertical dimension for component stacking and interconnection, the system achieves higher functionality density without proportionally increasing the planar area, thus resolving the contradiction between functionality and product size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple electrical parts and connections are implemented to increase functionality, then product features are improved, but the number of electrical parts on circuit boards increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidnumber of electrical parts
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple integrated circuit packages into a single stacked assembly, reducing the number of discrete electrical parts that need to be individually mounted and connected on circuit boards. The packages are interconnected through TSVs within the stack, consolidating multiple functions into one integrated unit and simplifying the overall system architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

By nesting multiple functional packages within a single stacked structure, the invention reduces the number of separate electrical components that must be managed on the circuit board level. The nested arrangement allows these components to work together as an integrated system, thereby improving functionality while reducing electrical part count.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Length of stationary object

If package thickness is reduced to decrease product size, then overall package size is reduced, but manufacturing precision and reliability become more challenging

Engineering Contradiction:
Improvepackage sizeVSAvoidmanufacturing precision
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent addresses the manufacturing precision challenge by moving critical interconnections into the vertical dimension through TSVs. This allows the horizontal footprint to be reduced while maintaining adequate thickness for reliable manufacturing. The vertical stacking approach enables compact packaging without sacrificing manufacturing feasibility, as the TSV interconnections can be precisely formed during the stacking process rather than requiring high-precision lateral alignment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8518752B2Integrated circuit packaging system with stackable package and method of manufacture thereof
Publication Date: 2013.08.27 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8518752B2 patent drawing
  • US8518752B2 patent drawing
  • US8518752B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side.