Stackable Leadless Semiconductor Packages with Vertical Bonding
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Solution Overview
Problem
Conventional semiconductor packages with fine pin pitches face challenges such as increased footprint, costly trimming tools, lead bending, and complex surface-mounting processes, while existing leadless packages like QFN and DFN require specialized materials and processes, limiting density and stacking capabilities.
Innovation Solution
A leadless three-dimensional stackable semiconductor package with substrate strips having mounting contacts on top, bottom, and sides, featuring a thinner inner portion for component attachment and exposed sidewalls for additional packaging, allowing for electrical connections and stacking of packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional plastic packages with leads are used to accommodate a large number of electrical connection points, then the number of external terminals increases, but the footprint of the package increases
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional packaging by adding vertical stacking capability. Packages can be stacked one on top of another using upper and lower surfaces for mounting, effectively increasing the number of external terminals without increasing the horizontal footprint area.
2Quantity of substance
If pin pitch is decreased to accommodate more pins without increasing footprint, then the number of terminals increases, but trimming costs increase and leads are prone to bending
Solution Approach 1:
The patent eliminates the perimeter leads entirely by extracting them from the package structure. Instead, electrical connections are made through land grid arrays on the package surfaces, which are more robust and do not require expensive trimming operations or precise alignment during surface-mounting.
3Quantity of substance
If surface-mounting of fine-pitch packages is performed, then electrical connections are established, but the process becomes costly and complicated due to critical alignment requirements
Solution Approach 1:
The patent uses land grid arrays with larger, more robust contact pads that are easier to align and solder. These simplified connection structures reduce the complexity and cost of the surface-mounting process by eliminating critical alignment requirements associated with fine-pitch leads.
4Ease of manufacture
If leadless packages like QFN and DFN are used, then perimeter leads are eliminated, but specialized packaging materials and processes are required, limiting density and stacking capabilities
Solution Approach 1:
The patent creates a universal package design with land grid arrays on both upper and lower surfaces, enabling the same package structure to be mounted in multiple orientations and stacked vertically. This multi-functional design eliminates the need for specialized packaging materials while providing both leadless construction and stacking capability.
Data Source
AI summary
An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. Three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires.