Stackable Memory Bit Cell With Laser Annealed Transistors
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Solution Overview
Problem
The challenge in vertically stacked memory devices, such as magnetic tunnel junctions (MTJs), is that processing for upper transistors can degrade the underlying memory devices during annealing, affecting magnetoresistance and overall performance.
Innovation Solution
The method involves forming a vertically stacked two-transistor (2T) one-memory device structure where the upper transistor is made from crystalline semiconductor material using laser annealing, which converts amorphous semiconductor material without damaging the underlying MTJ, enabling 3D multilayer stacking without degrading the memory cells or metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If annealing processes are applied to the upper transistor to form crystalline semiconductor material, then the transistor performance is improved, but the underlying memory device magnetoresistance degrades
Solution Approach 1:
The patent segments the annealing process into two distinct stages: a first annealing process for the lower transistor and a second annealing process for the upper transistor. Each annealing process has optimized temperature and time parameters that are tailored to the specific requirements of each transistor layer, allowing the upper transistor to achieve crystalline material formation while the lower memory device is protected from excessive thermal exposure that would cause magnetoresistance degradation
Solution Approach 2:
The patent applies preliminary action by performing the first annealing process on the lower transistor before forming the upper transistor. This preliminary annealing establishes a stable foundation and allows subsequent processing to be optimized without affecting the already-annealed lower transistor, thereby protecting the memory device from retroactive thermal damage
2Productivity
If vertical stacking of transistors over memory devices is implemented to increase density, then device integration is improved, but processing complexity increases
Solution Approach 1:
The patent divides the vertical stacking process into distinct sequential stages: forming the lower transistor, forming the memory device, and forming the upper transistor. Each stage has its own optimized processing parameters, allowing complex vertical integration to be achieved through manageable, independent process modules rather than a single complex simultaneous process
Solution Approach 2:
The patent employs preliminary action by completing the lower transistor formation and annealing before proceeding to memory device formation and upper transistor fabrication. This sequential preliminary action simplifies the overall processing by breaking down the complex vertical stacking task into manageable preliminary steps, each with optimized parameters that avoid compounding complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the magnetoresistance of the underlying memory device post-annealing, ensuring the performance of the MTJ remains unchanged, and allows for efficient 3D multilayer stacking without damaging the underlying structures.
Implementation Method 1
The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material
Implementation Method 2
The spin-transfer torque (STT) phenomenon is realized in an MTJ structure, wherein one ferromagnetic layer (referred to as 'magnetic free layer') has a non-fixed magnetization
Implementation Method 3
A basic structure of a magnetic tunnel junction includes two thin ferromagnetic layers separated by a thin insulating layer through which electrons can tunnel
Data Source
AI summary
A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.