Stackable Microelectronic Package Contact Arrangements
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Solution Overview
Problem
Conventional interconnecting methods for multiple microelectronic dies in memory package structures face complexity and performance issues, particularly in routing control and address signals which experience significant propagation delay due to lengthy signal paths.
Innovation Solution
The proposed solution involves a microelectronic assembly with a specific arrangement of contact structures on substrates, including concentric ring arrays and L-shaped regions, optimized for efficient interconnection of microelectronic dies to reduce signal path lengths and propagation delays, particularly for control and address signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional interconnecting methods are used for multiple microelectronic dies, then the package structure can be formed, but the signal path length becomes excessive causing propagation delay
Solution Approach 1:
The patent transitions from conventional 2D planar routing to a 3D vertical stacking architecture. Multiple microelectronic dies are stacked vertically with interconnect structures (through-silicon vias, redistribution layers) enabling three-dimensional signal routing. This dimensional change dramatically shortens signal paths by allowing direct vertical connections between adjacent dies, eliminating the need for lengthy lateral routing paths in conventional 2D layouts.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple dies are stacked and interconnected through redistribution layers and vias. The interconnect structure itself is nested within the substrate, with through-silicon vias penetrating through dies and redistribution layers routed within substrate layers. This nesting allows compact integration while maintaining short signal paths between functional blocks.
2Device complexity
If conventional interconnecting methods are used, then connections can be established, but the interconnection complexity increases significantly
Solution Approach 1:
The patent segments the interconnection function into distinct modular components: through-silicon vias for vertical penetration, redistribution layers for signal routing, and dedicated interconnect structures between dies. Each segment performs a specific function and can be independently optimized. This segmentation reduces overall complexity by breaking down the complex routing problem into manageable, standardized building blocks that can be systematically implemented.
3Loss of time
If lengthy signal paths are used for control and address signals, then all dies can be connected, but propagation delay increases
Solution Approach 1:
The patent applies local quality optimization by creating dedicated short signal paths for control and address signals through the 3D stack. Critical signals are routed through direct vertical via paths rather than lateral routes, and redistribution layers are configured to provide localized signal distribution. This ensures that time-sensitive control and address signals experience minimal propagation delay, while other signals can use longer paths without impacting overall performance.
Data Source
AI summary
An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.