Stackable Multi-Chip Package with Inter-Chip Structure
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Solution Overview
Problem
The electronics industry faces challenges in creating stackable multi-chip package systems that achieve low cost manufacturing, increased miniaturization, greater packaging densities, improved yield, and enhanced reliability, while maintaining a thin, high-density footprint, as existing solutions have not adequately addressed these needs.
Innovation Solution
A stackable multi-chip package system is designed with an inter-chip structure adjacent to an external interconnect, featuring dual land rows and L-shape external interconnects, where both integrated circuit dice are partially exposed and connected in a symmetrical configuration to allow for efficient stacking and thermal dissipation, with an encapsulation that covers internal interconnects while exposing external lands for connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor packages are made smaller and thinner to increase packaging density, then packaging density improves, but manufacturing complexity and cost increase
Solution Approach 1:
The package is divided into multiple segments including a lead frame segment, a semiconductor die segment, and an encapsulant segment. Each segment is manufactured separately and then assembled together, allowing for simplified individual manufacturing processes while achieving high packaging density through the stacked configuration of these segments.
Solution Approach 2:
The semiconductor die is nested within the encapsulant, which is in turn nested within the lead frame structure. This nested arrangement allows multiple components to be contained within a compact volume, increasing packaging density without proportionally increasing manufacturing complexity, as each nested element can be processed independently before assembly.
2Quantity of substance
If multiple semiconductor dies are stacked to increase packaging density, then packaging density improves, but manufacturing yield decreases
Solution Approach 1:
By segmenting the package into separately manufacturable components (lead frame, die, encapsulant), the manufacturing process is broken into independent stages. This allows each component to be manufactured and tested separately, improving yield by identifying and correcting defects at earlier stages rather than discovering them only after complete assembly of the stacked structure.
Solution Approach 2:
The lead frame and other structural components are prepared and pre-assembled before the semiconductor die is attached. This preliminary action allows for pre-testing and quality verification of the support structure, ensuring that the die mounting process can proceed efficiently with higher yield, as the foundation is already verified and ready.
3Reliability
If conventional molding processes are used to encapsulate multiple dies, then encapsulation is achieved, but package height increases
Solution Approach 1:
Instead of expanding the encapsulation horizontally to cover multiple dies (which would increase package footprint), the design stacks components vertically in the height dimension. The encapsulant is applied as a thin layer that covers the die and immediate interconnect structures, while the overall package height is controlled by the compact vertical arrangement of the lead frame, die, and encapsulant layers.
Solution Approach 2:
The encapsulant is applied as a thin film or shell that provides protective encapsulation without adding significant height. This thin-film approach allows the encapsulation function to be achieved with minimal vertical space, maintaining a low-profile package while still providing the necessary protection and environmental sealing for the stacked components.
Data Source
AI summary
A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip structure, connecting a second integrated circuit die and an inner portion of the base with the second integrated circuit die mounted under the inter-chip structure, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.