Stackable Phase Change Memory Cell With Integrated Heater

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Solution Overview

Problem

Conventional resistive non-volatile memories (NVMs) like PCRAMs require large programming currents, leading to large cell sizes, inefficient heating, and increased power consumption due to heat loss and proximity effects with heat sinks, which decreases reliability and increases power consumption.

Innovation Solution

A memory cell design with a cell selector and a cell stack layer comprising a phase change material, where bitline connection units act as heaters, reducing the need for large transistors and improving heating efficiency by minimizing heat loss and optimizing current requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional resistive NVMs use large programming currents to switch between resistive states, then the switching function is achieved, but the cell size becomes large and power consumption increases

Engineering Contradiction:
Improveswitching functionVSAvoidcell size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar memory cell layout to a three-dimensional stacked architecture. Multiple resistive elements are vertically stacked above a single selector transistor, allowing multiple storage units to share common bitlines and wordlines. This vertical stacking reduces the lateral footprint of each cell while maintaining the required switching function for each storage element.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The selector transistor serves multiple functions: it acts as the switching element for selecting the memory cell, and simultaneously functions as a heater to induce phase changes in the resistive elements. This multi-functionality eliminates the need for separate heater structures, reducing cell complexity and area while achieving both cell selection and state switching.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If conventional resistive NVMs use large programming currents, then state switching is achieved, but power consumption increases

Engineering Contradiction:
Improvestate switchingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the selector transistor and heater function into a single component. The same transistor that selects the memory cell by controlling current flow also serves as the heating element to induce phase changes in the resistive material. This integration reduces the total current requirement compared to separate selector and heater structures, thereby reducing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces thermal isolation structures (dielectric layers with low thermal conductivity) surrounding the resistive elements. These structures create localized thermal zones that confine heat to the intended resistive element, preventing heat diffusion to neighboring cells. This local thermal confinement allows for lower programming currents while maintaining effective heating of the target element, thus reducing overall power consumption.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If memory elements are disposed in close proximity with heat sinks (metal lines and electrodes), then electrical connectivity is achieved, but heat loss increases and heating efficiency decreases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidheat loss
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent introduces thermal isolation structures (dielectric layers with low thermal conductivity) surrounding the resistive elements and heaters. These structures create localized thermal zones that confine heat to the intended resistive element, preventing heat diffusion to neighboring cells and heat sinks. This local thermal confinement maintains electrical connectivity while significantly reducing parasitic heat loss to surrounding metal lines and electrodes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces dielectric layers as thermal intermediaries between the resistive elements/heaters and the surrounding metal lines and electrodes. These dielectric layers act as thermal barriers that block heat transfer to heat sinks while allowing electrical connections to be maintained through other pathways. This intermediary structure effectively decouples the thermal and electrical pathways, reducing heat loss without compromising electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enables more reliable and efficient resistive NVMs with reduced power consumption and smaller cell sizes, enhancing performance and density by optimizing heating and current usage.

Implementation Method 1

The switching between the states involves switching between an amorphous to a crystalline phase. The switching between two phases is achieved by heating the memory element using a heater.

Methodology Applied
Scientific EffectPhase change: Phase Change

Implementation Method 2

The cell stack connectors serve as heaters for the cell stack layer.

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS9196356B2Stackable non-volatile memory
Publication Date: 2015.11.24 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US9196356B2 patent drawing
  • US9196356B2 patent drawing
  • US9196356B2 patent drawing

AI summary

A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.