Stackable Semiconductor Assemblies With Molded Wafer Trenches
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Solution Overview
Problem
Current semiconductor packaging techniques, such as wafer level packaging (WLP), face challenges in accommodating high pin counts and high input/output requirements due to space limitations, leading to increased complexity and cost, as well as inconsistent electrical connections and processing time issues with via formation and plating.
Innovation Solution
The method involves forming semiconductor assemblies with molded wafers that include trenches and channels to create lateral contacts and redistribution structures, allowing for simultaneous processing and reduced complexity in forming interconnects, which are then stacked and connected using lead frames for enhanced electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer level packaging (WLP) is used to reduce package size, then the form factor is minimized and electrical performance is improved, but the number of interconnect elements is restricted due to footprint limitations
Solution Approach 1:
The patent transitions from planar interconnect arrangement (2D) to three-dimensional stacked architecture (3D), allowing interconnect elements to be arranged in multiple layers vertically above the die footprint, thereby increasing the number of interconnects without increasing the package footprint
2Quantity of substance
If interconnects are positioned outside the die footprint to increase interconnect number and pitch, then interconnect capacity is improved, but processing complexity and cost significantly increase
Solution Approach 1:
The patent performs preliminary formation of through-mold vias and redistribution layers on the wafer before dicing, allowing subsequent stacking and interconnection to be simplified. The preliminary wafer-level processing establishes the interconnect architecture in advance, reducing the complexity of final assembly operations
Solution Approach 2:
The patent divides the packaging process into separate stages: wafer-level interconnect formation, dicing, and subsequent stacking. This segmentation allows each stage to be optimized independently, reducing overall processing complexity while achieving high interconnect counts
3Manufacturing precision
If sequential via formation by ablation or drilling is used, then via formation is achieved, but processing time significantly increases
Solution Approach 1:
The patent merges multiple individual via formation operations into a single parallel etching process that forms all through-mold vias simultaneously across the wafer surface, dramatically increasing productivity while maintaining via quality through controlled etching parameters
4Productivity
If etching process is used to simultaneously form vias, then processing speed is improved, but via size consistency and dense distribution are compromised
Solution Approach 1:
The patent optimizes etching process parameters including etchant composition, temperature, and exposure time to achieve uniform via dimensions and consistent electrical characteristics across all vias formed in parallel, while maintaining high processing speed through efficient chemistry and process control
Data Source
AI summary
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.