Stackable Semiconductor Die with Peripheral Conductive Vias

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Solution Overview

Problem

Current through-hole via (THV) technology in semiconductor devices limits the placement of additional circuitry within the device and reduces yields due to the need for wider saw streets when vias are located outside the die, restricting the integration of different functionalities and increasing package size.

Innovation Solution

A method for creating stackable semiconductor devices using THVs, where conductive vias are formed through an insulating layer around each semiconductor die, allowing for electrical connection between adjacent dies, and the use of organic materials like benzocyclobutene to accommodate multiple rows of vias, enabling flexible stacking configurations and increased yield without size constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a via is located within a semiconductor device, then the device can be made compact, but the freedom of having additional circuitry within the semiconductor device is restricted

Engineering Contradiction:
Improvepackage sizeVSAvoidfunctionality
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent divides the via structure into two distinct parts: vias formed within the die (for compactness) and vias formed in the organic material surrounding the die (for additional circuitry). This segmentation allows each via location to serve different purposes, resolving the contradiction between compactness and functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends the via formation process into a new dimension by forming vias in the organic material layer that surrounds the die, rather than only within the die itself. This additional spatial dimension provides extra room for circuitry without increasing the die size, thus maintaining compactness while enhancing functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If a via is located outside the semiconductor device along the saw street guide, then additional circuitry can be accommodated, but a wider saw street is required which reduces yields

Engineering Contradiction:
ImprovefunctionalityVSAvoidyield
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies different via formation approaches to different locations: vias within the die use one method, while vias in the surrounding organic material use another method. This local differentiation allows via formation in the organic material region without requiring wider saw streets, thus maintaining high yield while accommodating additional circuitry.

Inventive Principle:
Principle #3Local quality

3Device complexity

If traditional THV technology is used, then the structure is simple, but the integration of devices with different functionality within a respective package is limited

Engineering Contradiction:
ImprovestructureVSAvoidintegration capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal via structure that can serve multiple functions: vias within the die provide compact interconnects, while vias in the surrounding organic material enable additional circuitry and different functionality integration. This multi-functional via system resolves the contradiction between structural simplicity and integration capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8062929B2Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die
Publication Date: 2011.11.22 JCET SEMICON (SHAOXING) CO LTD
  • US8062929B2 patent drawing
  • US8062929B2 patent drawing
  • US8062929B2 patent drawing

AI summary

A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.