Stackable Semiconductor Device with Metal Pillars
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices and manufacturing methods suffer from low sensitivity, high cost, decreased reliability, and large package sizes, limiting their performance and efficiency.
Innovation Solution
A semiconductor device with a stackable design featuring small size and fine pitch pattern spacing, comprising a substrate, semiconductor die, metal pillars, and an encapsulant, manufactured using a method that includes forming metal pillars on a carrier substrate, coupling them to a substrate, and encapsulating them with an encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor device structures are used, then manufacturing processes are simpler, but package size becomes too large
Solution Approach 1:
The patent transitions from planar two-dimensional device layout to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically with interposer layers and redistribution layers, enabling compact package size by utilizing the vertical dimension for device integration rather than expanding horizontally.
Solution Approach 2:
The patent implements a nested structure where semiconductor dies are stacked within a package cavity, with each die nested on top of the previous one. The interposer layers and encapsulant material further nest around and protect the stacked dies, creating a compact hierarchical arrangement that reduces overall package volume.
2Manufacturing precision
If finer pitch pattern spacing is implemented, then device integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the device into multiple separate semiconductor dies that are individually manufactured with standard pitch patterns, then stacked vertically. This segmentation allows each die to be manufactured with relaxed precision requirements, while the overall system achieves high integration density through the stacked arrangement of multiple dies.
Solution Approach 2:
The patent introduces interposer layers and redistribution layers as intermediary structures between stacked dies. These intermediaries provide alignment references and signal routing that facilitate precise positioning of fine pitch patterns on each die while maintaining manufacturability through standardized manufacturing processes for each individual die.
3Reliability
If stackable design with fine pitch is used, then connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent employs universal interposer layers and redistribution layer structures that serve multiple functions: providing mechanical support, enabling electrical connectivity between stacked dies, facilitating thermal management, and offering alignment references. This multi-functionality reduces the need for separate specialized components, thereby managing complexity while enhancing reliability and connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of semiconductor devices with a smaller footprint, improved reliability, and enhanced connectivity, allowing for efficient stacking and reduced overall size while maintaining fine pitch pattern spacing.
Implementation Method 1
forming metal pillars on a carrier substrate
Implementation Method 2
forming metal pillars on a carrier substrate
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.