Stackable Timer Blocks With Programmable Cross-Trigger Coupling
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Solution Overview
Problem
The increasing complexity of system-on-a-chip (SoC) designs necessitates a more efficient way to combine timer IP blocks with varying capture-compare channels, as using larger-than-needed timers is resource-inefficient, while smaller timers limit capabilities, and testing each IP block individually is cumbersome.
Innovation Solution
A stackable base timer circuit combined with a programmable trigger matrix and fault cross-trigger matrix allows for the creation of timers with increased capabilities by coupling multiple base timer circuits, enabling flexible configuration and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single large-capability timer IP block is used to satisfy all possible capture-compare channel needs, then all capability requirements are met, but resource utilization becomes inefficient when fewer channels are needed
Solution Approach 1:
The patent divides the timer functionality into multiple stackable base timer circuit blocks, each providing a fixed number of capture-compare channels (e.g., two channels per block). These blocks can be individually selected and combined to match the specific channel requirements of different applications, avoiding the resource waste of using a single oversized timer block.
Solution Approach 2:
The base timer circuit block is designed as a universal modular unit that can be replicated and stacked to create timers with varying channel capacities. The same base block design serves multiple purposes across different applications by simply changing the number of blocks stacked together, providing both adaptability and resource efficiency.
2Loss of energy
If multiple different timer IP blocks with varying capture-compare channels are provided to match specific needs, then resource utilization is optimized, but device complexity and verification burden increase
Solution Approach 1:
Instead of creating multiple complete timer IP blocks with different channel counts, the patent segments the timer functionality into identical base blocks that can be stacked. This reduces the number of unique IP block designs from many variants to a single reusable base unit.
Solution Approach 2:
Multiple identical base timer blocks are merged together through stacking to create the desired channel capacity. The merging is achieved through standardized interconnection interfaces that allow base blocks to be combined in series, providing different channel capacities using the same fundamental building block.
3Adaptability or versatility
If multiple different timer IP blocks are used in an SoC, then specific channel requirements are met, but testing and verification of each IP block becomes cumbersome
Solution Approach 1:
The verification process is segmented into verifying a single base timer block design rather than multiple different timer IP blocks. Since all base blocks are identical, verifying one instance verifies all instances, dramatically reducing the total verification time and effort required.
Solution Approach 2:
All base timer blocks use the same homogeneous design and interface specifications, which simplifies the verification process. The uniformity across all blocks means that testing procedures, validation methods, and verification protocols need to be developed only once for the base block design.
Data Source
AI summary
An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.