Stackable Timer Circuits With Programmable Trigger Matrix
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Solution Overview
Problem
The increasing complexity of system-on-a-chip (SoC) designs necessitates a flexible and efficient approach to provide timers with varying capture-compare channels, as existing IP blocks often require either oversized or undersized timer circuits, leading to resource inefficiency and increased verification needs.
Innovation Solution
A stackable base timer circuit combined with a programmable trigger matrix and fault cross-trigger matrix allows for the creation of timers with increased capabilities by coupling multiple base timer circuits, enabling the formation of a single timer with desired functionality and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple different timer IP blocks are used to accommodate varying channel requirements, then the capability to meet specific channel needs is improved, but the device complexity and verification burden increase
Solution Approach 1:
The timer circuit is divided into multiple identical base timer blocks, each with a fixed number of capture-compare channels. These segmented blocks can be selectively instantiated and stacked to achieve the desired total channel count, replacing the need for multiple different timer IP blocks with various channel configurations.
Solution Approach 2:
A single base timer block design serves multiple functions by being replicated and stacked in different quantities. The same universal base timer IP block can provide 2, 4, 6, 8, or more channels depending on how many instances are instantiated, eliminating the need for multiple specialized timer IP blocks.
2Adaptability or versatility
If a timer with more capture-compare channels is used to accommodate future needs, then the capability to meet increasing channel requirements is improved, but the resource utilization efficiency deteriorates
Solution Approach 1:
The timer configuration becomes dynamic rather than static. Instead of committing to a fixed large-capacity timer, the system can dynamically instantiate the appropriate number of base timer blocks based on actual channel requirements, allowing resource allocation to match demand and improve utilization efficiency.
Solution Approach 2:
The total channel capacity parameter can be changed by varying the number of base timer block instances. This allows the timer capacity to be adjusted according to specific application needs, preventing over-provisioning and improving resource utilization while maintaining the ability to scale when needed.
3Reliability
If multiple different timer IP blocks are verified and tested, then the coverage of different timer configurations is improved, but the verification time and effort increase
Solution Approach 1:
Instead of verifying multiple different timer IP block designs, the verification process needs to be performed only once on the single base timer block design. Once verified, this validated design can be copied and instantiated multiple times, inheriting the verification status and eliminating redundant verification efforts.
Data Source
AI summary
An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.