Stacked 2D-Channel Planar FETs for High Current Density Scaling
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Solution Overview
Problem
Existing 2D channel transistors face challenges in achieving high current density and scaling due to short channel effects and quantum confinement, limiting their performance in high-density applications.
Innovation Solution
The development of a stacked, planar, 2D-channel field effect transistor (FET) configuration, which includes multiple layers of 2D channel materials supported by dielectric bridges and gate dielectric layers, enhancing current density and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 2D channel transistor structures are used, then fabrication is simpler, but current density is limited and short channel effects dominate
Solution Approach 1:
The patent transitions from planar 2D channel transistors to vertically stacked 3D structures with multiple channel layers stacked along the vertical axis. This dimensional change increases the effective channel area without increasing the footprint, thereby improving current density while maintaining scalability and reducing short channel effects through the vertical gate control architecture.
Solution Approach 2:
The patent implements multiple channel layers nested vertically within a compact structure, where each channel layer is surrounded by gate structures. This nested arrangement allows multiple active channels to be packed into a small volume, increasing current density while maintaining effective gate control over each channel to mitigate short channel effects.
2Productivity
If gate length is scaled down to increase density, then device density improves, but short channel effects worsen
Solution Approach 1:
By stacking multiple channel layers vertically, the patent achieves higher device density without further reducing the gate length in the lateral dimension. The vertical stacking provides additional current pathways while maintaining longer effective gate lengths, thus improving density without exacerbating short channel effects.
Solution Approach 2:
The patent divides the channel into multiple separate layers, each controlled by its own gate structure. This segmentation allows each channel layer to be independently optimized with appropriate gate lengths, achieving high overall density while each segment maintains good electrostatic control to minimize short channel effects.
3Productivity
If multiple channel layers are stacked to increase current density, then current density improves, but device complexity increases
Solution Approach 1:
The patent divides the transistor into multiple identical or similar channel layers stacked vertically, each with its own gate structure. This segmentation into repeating units simplifies the fabrication process through pattern replication and allows independent optimization of each layer, achieving high current density while managing complexity through modular design.
Solution Approach 2:
The stacked channel layers serve multiple functions: they provide parallel current pathways for high current density, enable independent gate control for each layer to manage short channel effects, and create a scalable architecture where the number of layers can be adjusted based on performance requirements.
Data Source
AI summary
A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.