Stacked 2D Semiconductor Shell Channels for Low Drive Current

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Solution Overview

Problem

Two-dimensional (2D) semiconductor channels suffer from low drive current, limiting their performance in advanced semiconductor devices, particularly for gate lengths below 10 nm, due to increased short channel effects.

Innovation Solution

The formation of stacked 2D semiconductor channels using sacrificial nanowires or nanoribbons, where a gate stack is disposed over the nanowires, etched out to create voids, and 2D semiconductor channels are grown as shells within these voids, which can be air-filled or dielectric-filled, enhancing drive currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 2D semiconductor channels are used for scaling, then short channel effects are improved, but drive current becomes low

Engineering Contradiction:
Improveshort channel effectsVSAvoiddrive current
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent transitions from planar 2D semiconductor channels to vertically stacked 3D semiconductor shells. By growing multiple semiconductor layers vertically around a sacrificial nanowire core, the device achieves enhanced drive current through increased effective channel width while maintaining the superior short channel control of 2D materials. This dimensional transition from 2D to 3D stacking directly resolves the contradiction between low drive current and short channel effects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs a nested structure where semiconductor shells are grown around a sacrificial nanowire core. The final structure consists of concentric semiconductor layers nested within a gate stack, with the gate dielectric and electrode surrounding the semiconductor shells. This nested architecture enables multiple semiconductor channels to be stacked vertically, increasing drive current while maintaining excellent electrostatic control for suppressing short channel effects.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If transistor dimensions are reduced, then device density is increased, but manufacturing constraints become overwhelming

Engineering Contradiction:
Improvedevice densityVSAvoidmanufacturing constraints
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent uses sacrificial nanowires and nanoribbons as preliminary structures that are formed first, then semiconductor shells are grown around them using chemical vapor deposition. The sacrificial structures are subsequently removed, leaving behind precisely formed semiconductor channels. This preliminary action approach simplifies the manufacturing of complex stacked structures by breaking down the process into manageable steps: forming sacrificial templates, growing shells, and removing templates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial nanowires and nanoribbons serve as intermediary structures that facilitate the formation of the final semiconductor device. These temporary structures enable precise positioning and shaping of the semiconductor shells during fabrication, then are removed after serving their purpose. This intermediary approach makes the manufacturing of complex stacked semiconductor structures more manageable and scalable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly enhances drive currents in 2D semiconductor devices, making them suitable for advanced semiconductor applications by mitigating short channel effects and improving performance at smaller dimensions.

Implementation Method 1

2D semiconductor channels are grown as shells within these voids

Methodology Applied
Scientific EffectVapor-phase deposition: Physical Vapour Deposition

Data Source

PatentUS11935956B2TMD inverted nanowire integration
Publication Date: 2024.03.19 INTEL CORP
  • US11935956B2 patent drawing
  • US11935956B2 patent drawing
  • US11935956B2 patent drawing

AI summary

Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.