Stacked 2DEG Transistor Structure for Lower On-Resistance
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Solution Overview
Problem
Existing transistors using silicon face limitations in conducting high power and efficiency, while wider bandgap semiconductor materials like SiC, AlN, and GaN can form two-dimensional electron gases (2DEGs) for improved conductivity, but existing structures do not effectively utilize multiple 2DEGs to reduce on-resistance and enable independent control.
Innovation Solution
A transistor structure with multiple heterojunction layer sets inducing stacked 2DEGs, utilizing conductive paths below the surface-level 2DEG and allowing gate control above, enabling reduced on-resistance and independent or coordinated control of multiple transistors sharing a common source and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single 2DEG channel is used in wide bandgap semiconductor transistors, then the transistor can conduct higher power than silicon, but the on-resistance remains too high for optimal efficiency
Solution Approach 1:
The invention divides the single channel into multiple stacked 2DEG channels (first 2DEG in first channel layer, second 2DEG in second channel layer) separated by a barrier layer. Each 2DEG acts as an independent conduction path, and the combined effect reduces overall on-resistance while maintaining high power capability. The segmentation allows parallel current flow through multiple channels.
Solution Approach 2:
The invention transitions from a single two-dimensional channel to multiple stacked two-dimensional channels in the vertical dimension. By stacking 2DEGs at different depths (first 2DEG above second 2DEG) and connecting them via vertical conductive paths (source plug, drain plug), the device utilizes the third dimension to create parallel conduction paths without increasing lateral footprint.
2Reliability
If multiple 2DEG channels are stacked vertically, then on-resistance is reduced, but the device structure becomes more complex
Solution Approach 1:
The structure nests multiple heterojunction layer sets within each other in a vertical stack. Each heterojunction layer set (barrier layer + channel layer forming a 2DEG) is nested within the overall transistor structure, with barrier layers and channel layers alternating vertically. This nested arrangement compactly integrates multiple functional channels without requiring lateral expansion.
Solution Approach 2:
The stacked 2DEG structure serves multiple functions simultaneously: it provides parallel conduction paths for reduced on-resistance, maintains high breakdown voltage through the wide bandgap materials, and enables independent control of each channel through selective gating. The same structural framework achieves both low resistance and high voltage capability.
3Reliability
If multiple transistors are integrated to reduce resistance, then conductivity improves, but the device area and control complexity increase
Solution Approach 1:
Instead of placing multiple transistors side-by-side in the lateral plane (increasing area), the invention stacks 2DEG channels vertically in the third dimension. Multiple conduction paths are achieved by stacking channel layers (first channel layer, second channel layer) with barrier layers between them, connected by vertical source and drain plugs, thereby maintaining compact lateral footprint while multiplying conduction capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure significantly reduces on-resistance and allows for independent or simultaneous operation of multiple transistors, enhancing conductivity and control capabilities.
Implementation Method 1
a first heterojunction formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer, the first heterojunction inducing a first two-dimensional electron gas (2DEG) within the first channel semiconductor layer
Data Source
AI summary
A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.