Stacked 2T DRAM Structure for Low-Leakage Data Retention
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Solution Overview
Problem
Existing DRAM devices face challenges in maintaining data retention due to capacitor leakage, requiring external refresh circuits and having a large footprint, which increases power consumption and limits integration in high-density circuits.
Innovation Solution
A semiconductor structure is developed with a vertical transistor stacked on a nanosheet transistor, utilizing indium-gallium-zinc-oxide (IGZO) in the channel region and a unique connection between the transistors to reduce leakage current and footprint, forming a dynamic random-access-memory (DRAM) device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external refresh circuits are used to prevent capacitor charge leakage, then data retention is improved, but device footprint and power consumption increase
Solution Approach 1:
The patent combines the write transistor and read transistor into a shared structure where the write transistor's source/drain serves dual purposes: as source/drain for write operations and as the storage node capacitor for data retention. This merging eliminates the need for separate external refresh circuits while maintaining data retention capability.
Solution Approach 2:
The write transistor is designed to perform multiple functions: it acts as the write access transistor during write operations and simultaneously serves as the storage element (capacitor) for data retention during read operations. This multi-functionality reduces the overall device footprint by eliminating dedicated refresh circuitry.
2Reliability
If external refresh circuits are used to prevent capacitor charge leakage, then data retention is improved, but power consumption increases
Solution Approach 1:
By merging the write transistor with the storage function, the patent eliminates the need for continuous operation of separate refresh circuits. The shared transistor structure reduces power consumption by only activating the write transistor when needed for either write or read operations, rather than requiring continuous refresh cycles.
Solution Approach 2:
The write transistor automatically serves as the storage element, eliminating the need for external refresh circuits that would continuously consume power. The structure itself provides the data retention function without requiring additional active management circuits.
3Ease of manufacture
If conventional planar transistor layout is used, then manufacturing is simpler, but device footprint is larger
Solution Approach 1:
The patent transitions from a conventional planar (2D) transistor layout to a vertical (3D) stacked architecture. The write transistor is positioned vertically above the read transistor, with the write transistor's source/drain extending down to contact the read transistor's gate. This vertical stacking dramatically reduces the lateral footprint while maintaining manufacturability through standard semiconductor fabrication processes.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.