Vertically Stacked 3T-1C Memory Cell for High Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3T-1C memory cell configurations face challenges in integrating into highly-integrated modern memory architectures due to their increased component count, which hinders scalability compared to 1T-1C configurations, and the difficulty in incorporating high-capacitance capacitors in 1T-1C configurations.
Innovation Solution
The proposed solution involves vertically stacking two or more components, including transistors and a capacitor, to increase integration density, with specific configurations where transistors T2 and T3 are stacked over transistor T1, and the capacitor is positioned to optimize charge storage and bitline operations, allowing for reduced capacitance needs and increased scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3T-1C memory cell configuration is used to reduce capacitance requirements, then lower capacitance can be utilized, but device complexity increases due to three transistors instead of one
Solution Approach 1:
The patent transitions from planar layout to vertical stacking, arranging the three transistors and capacitor in a three-dimensional configuration where T1 is at the bottom, T2 and T3 are stacked above it, and the capacitor is positioned laterally. This vertical dimension reduces the footprint area while maintaining the 3T-1C functionality, effectively addressing the device complexity issue by compacting the structure.
Solution Approach 2:
The patent implements a nested arrangement where transistor T2 is positioned above T1, and T3 is positioned above T2, creating a vertical stack. The capacitor is then laterally displaced and positioned adjacent to this stack. This nesting approach allows multiple components to occupy overlapping horizontal spaces, reducing the overall device area and making the complex 3T-1C configuration more suitable for highly-integrated architectures.
2Device complexity
If 1T-1C memory cell configuration is used for simplicity, then device complexity is reduced, but it becomes difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures
Solution Approach 1:
By stacking transistors vertically and positioning the capacitor laterally adjacent to the stack, the patent creates a three-dimensional structure that increases integration density. This vertical arrangement allows the capacitor to be positioned closer to the transistor gates, improving coupling efficiency and enabling sufficient capacitance values within a compact footprint suitable for highly-integrated architectures.
Solution Approach 2:
The patent optimizes the local arrangement by positioning the capacitor specifically adjacent to the lateral face of the transistor stack, rather than using a generic layout. This localized positioning maximizes the electric field coupling between the capacitor and the transistor gates, ensuring sufficient capacitance is achieved while maintaining high integration density.
3Productivity
If vertical stacking of components is implemented to increase integration density, then scalability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory cell into distinct functional segments: the vertical transistor stack (T1, T2, T3) and the laterally positioned capacitor. This segmentation allows each component to be formed and positioned independently with standardized processes, reducing the cumulative alignment errors that would occur in fully integrated monolithic structures. The clear spatial separation between the stack and capacitor simplifies the manufacturing precision requirements compared to fully interleaved configurations.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.