Stacked Accelerator Memory Structure for Low-Power AI Data Retention
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Solution Overview
Problem
Semiconductor devices with accelerators face issues of high power consumption, heat generation, increased size, and frequent data transfers due to limited storage capacity and parasitic capacitance in wiring, especially in AI technology applications.
Innovation Solution
The semiconductor device incorporates a CPU and an accelerator with distinct memory circuits and transistors, including OS transistors with metal oxides in the channel formation region, allowing for stacked memory layers and low-power data retention, reducing parasitic capacitance and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the accelerator has large storage capacity for retaining weight data, then data transfer frequency is reduced, but device size increases
Solution Approach 1:
The patent merges the storage function with the accelerator by integrating memory circuits directly into the accelerator structure, allowing weight data to be retained locally without requiring separate large-capacity storage devices, thus reducing data transfer frequency while avoiding significant device size increase
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacked structure, placing memory circuits in different layers above the accelerator core. This vertical stacking enables increased storage capacity without proportionally increasing the device footprint, effectively resolving the contradiction between storage capacity and device size
2Speed
If high-speed data transmission is implemented, then data transfer performance is improved, but parasitic capacitance and resistance in wiring increase power consumption
Solution Approach 1:
The patent extracts the memory function from distant storage devices and places it directly within the accelerator structure. This eliminates long wiring paths, removing the source of parasitic capacitance and resistance that cause power consumption, while still enabling high-speed data transmission between the memory circuits and arithmetic units
Solution Approach 2:
The patent introduces intermediate memory circuits as buffers between the external memory and the arithmetic units. These intermediate circuits reduce the distance and complexity of data transmission paths, thereby reducing parasitic effects and power consumption while maintaining high-speed transfer capability
3Productivity
If AI technology with large amount of calculation is implemented, then processing capability is improved, but heat generation and power consumption increase
Solution Approach 1:
The patent segments the accelerator into multiple functional blocks, each with dedicated memory circuits. This segmentation allows for localized data processing and reduces the need for long-distance data transmission across the entire accelerator, thereby reducing overall power consumption and heat generation while maintaining high processing capability
Solution Approach 2:
The patent uses three-dimensional stacking to place memory circuits vertically above arithmetic units. This reduces the horizontal wiring distance and associated power consumption, enabling high-performance AI processing with reduced heat generation compared to traditional planar architectures
4Use of energy by moving object
If distance between weight data storage chip and accelerator is reduced, then parasitic capacitance and resistance are reduced, but device integration complexity increases
Solution Approach 1:
The patent combines the storage chip and accelerator into a single integrated device with memory circuits built directly on the same substrate. This eliminates the need for separate chips and complex inter-chip connections, reducing parasitic effects and power consumption while managing integration complexity through systematic design
Data Source
AI summary
To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.