Vertically Stacked Active Device for Display Aperture Ratio
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Solution Overview
Problem
Current display panels face challenges in achieving high resolution and aperture ratio due to limitations in designing various types of active devices without compromising the panel's aperture ratio.
Innovation Solution
The implementation of a vertically stacked circuit design that combines poly-silicon semiconductor and oxide semiconductor layers, sharing a gate electrode, to enhance space utilization and increase aperture ratio while achieving a narrow frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single type of active device is used in the display panel, then the device structure is simple and easy to manufacture, but the aperture ratio cannot be increased and high resolution cannot be achieved
Solution Approach 1:
The patent transitions from a planar arrangement of active devices to a vertically stacked three-dimensional configuration. Multiple semiconductor layers (first and second semiconductor layers with different material compositions) are stacked along the vertical direction, allowing circuit elements to occupy space in the third dimension rather than only in the planar area, thereby increasing the aperture ratio while maintaining manufacturing feasibility
Solution Approach 2:
The patent employs composite material structures by combining different semiconductor materials (e.g., oxide semiconductor and non-oxide semiconductor, or different poly-silicon layers with different doping concentrations) within the stacked architecture. This composite approach enables simultaneous optimization of electron mobility, threshold voltage control, and leakage current suppression, resolving the contradiction between device performance and aperture ratio
2Manufacturing precision
If various types of active devices are designed in the display panel to achieve high resolution, then the resolution improves, but the aperture ratio is affected and cannot be maintained
Solution Approach 1:
By stacking multiple active device layers vertically, the patent accommodates complex circuit functions (required for high resolution) in the vertical dimension rather than expanding horizontally. This allows multiple transistor types and circuit elements to coexist in a compact footprint, achieving high resolution without sacrificing aperture ratio
Solution Approach 2:
The stacked active device structure serves multiple functions simultaneously: the lower semiconductor layer provides threshold voltage control and the upper layer provides high electron mobility, or different layers serve as drive transistors, switching transistors, and compensation transistors. This multi-functionality consolidates what would otherwise require separate planar devices into a compact vertical stack, maintaining aperture ratio while enabling high resolution
3Reliability
If the active device structure is expanded to improve performance, then electron mobility and other electrical characteristics improve, but the device occupies more space and the frame cannot be narrowed
Solution Approach 1:
The patent achieves improved electron mobility and electrical characteristics by stacking semiconductor layers vertically rather than expanding the lateral dimensions of individual devices. The vertical stacking allows multiple functional layers to occupy minimal planar area while providing enhanced electrical performance through the combined effects of the stacked structure
Solution Approach 2:
The patent implements a nested structure where one semiconductor layer is positioned above another, with gate electrodes and insulating layers interleaved between them. This nested arrangement allows the active device to achieve complex electrical characteristics (high electron mobility, controlled threshold voltage, low leakage) by nesting multiple functional elements within a compact vertical footprint, minimizing the device area for the frame
Data Source
AI summary
An active device includes a poly-silicon semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a first through hole, an oxide semiconductor layer, a first electrode and a second electrode. The poly-silicon semiconductor layer includes a first doped region, a channel region and a second doped region. The gate electrode is disposed on the first insulating layer covering the poly-silicon semiconductor layer, and corresponds to the channel region. The gate electrode is covered by the second insulating layer, where the first and second insulating layers have a first through hole. The oxide semiconductor layer is disposed on the second insulating layer and corresponds to the gate electrode. The first and second electrodes are oppositely disposed on the oxide semiconductor layer. The oxide semiconductor layer is electrically connected to the second electrode, and to the second doped region via the first through hole.