Stacked A/D Capacitor Layout for High-Accuracy Image Sensors
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Solution Overview
Problem
Existing image sensors face challenges in increasing chip area due to the arrangement of multiple elements, which affects the resolution and accuracy of A/D conversion without compromising the opening ratio of pixels.
Innovation Solution
The image sensor employs a laminated structure with separate substrates for capacitors in the A/D conversion unit, allowing for the arrangement of capacitors without increasing chip area, enhancing resolution and reducing the influence of parasitic capacitance for high-accuracy conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple elements are disposed in a conventional image sensor, then the chip area increases, but the resolution and accuracy of A/D conversion deteriorate
Solution Approach 1:
The patent applies three-dimensional stacking technology to arrange capacitors in different layers (first circuit layer and second circuit layer) rather than spreading them out in a single plane. This vertical arrangement in the depth dimension allows multiple capacitors to coexist without increasing the horizontal chip area, thereby maintaining compact form factor while enabling high-precision A/D conversion through multiple capacitor elements.
Solution Approach 2:
The patent segments the capacitor arrangement into distinct functional groups located in different circuit layers. The first capacitor is placed in the first circuit layer while the second capacitor is placed in the second circuit layer, creating spatially separated but electrically connected segments. This segmentation allows independent optimization of each capacitor's position and reduces parasitic capacitance interference between them.
2Measurement precision
If capacitors are arranged to enhance A/D conversion resolution, then parasitic capacitance influence increases, but conversion accuracy deteriorates
Solution Approach 1:
By moving capacitor arrangement from a two-dimensional plane to a three-dimensional stacked structure, the patent increases the physical distance between capacitor elements in the horizontal plane. This spatial separation in the vertical dimension reduces electromagnetic coupling and parasitic capacitance effects between capacitors, allowing higher resolution A/D conversion with reduced conversion errors due to differential non-linearity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the enhancement of A/D conversion resolution without increasing chip area, maintaining pixel opening ratio and reducing conversion errors due to differential non-linearity, thereby implementing highly accurate image sensing.
Implementation Method 1
a photoelectric conversion unit that photoelectrically converts incident light and generates a charge
Data Source
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AI summary
An image sensor includes: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts the analog signal generated due to charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal and a first circuit layer including a first capacitor for generating the reference signal and a second circuit layer laminated to the first circuit layer and including with a second capacitor for generating the reference signal.