Mixed-Polarity Stacked Amplifier Biasing for Voltage Compliance
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Solution Overview
Problem
RF amplifiers with mixed polarity transistor stacks face challenges in maintaining voltage compliance across transistors of different polarities, leading to potential malfunction or damage due to shifts in voltage at common nodes and variations in PVT characteristics.
Innovation Solution
A circuital arrangement and method for biasing stacked transistor amplifiers with N-type and P-type transistor stacks, utilizing a gate biasing circuit with N-type and P-type current mirrors, and a feedback loop to adjust gate biasing voltages based on the voltage at the common node, ensuring stable voltage compliance across all transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate biasing voltages are adjusted to control bias current through mixed polarity transistor stacks, then the amplifier can operate in different modes (idle/standby and active), but voltage shifts at common nodes may occur due to different I-V characteristics and PVT variations, potentially causing malfunction or damage to transistors
Solution Approach 1:
The patent implements a feedback mechanism where the voltage at the common node between N-type and P-type transistor stacks is continuously monitored. Based on this feedback, the gate biasing voltages are dynamically adjusted to compensate for voltage shifts caused by different I-V characteristics and PVT variations. This ensures that both stacks remain within their safe operating voltage ranges while enabling mode switching between idle/standby and active operation.
2Reliability
If different polarity transistors are used in stacked configurations to achieve push-pull topologies with improved linearity and noise figure performance, then RF amplifier performance is enhanced, but the different I-V characteristics and PVT variations of different polarity transistors cause voltage shifts at common nodes, affecting voltage compliance
Solution Approach 1:
The feedback loop continuously monitors the common node voltage and dynamically adjusts the gate biasing voltages of both N-type and P-type stacks to compensate for voltage shifts arising from different I-V characteristics and PVT variations. This maintains stable voltage distribution across the mixed polarity transistor stacks while preserving the performance benefits of push-pull topology.
Solution Approach 2:
The patent dynamically changes the gate biasing voltage parameters of the transistor stacks based on the monitored common node voltage and desired operating mode. By adjusting these voltage parameters in real-time, the system compensates for the inherent differences in I-V characteristics and PVT variations between different polarity transistors, maintaining stable voltage distribution and compliance.
Data Source
AI summary
Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.