Stacked Power Amplifier Output Stage With Harmonic Gate Biasing
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Solution Overview
Problem
Power amplifiers face challenges in maintaining desired characteristics due to voltage stress, which can lead to transistor degradation and inefficiency, particularly in integrated CMOS technologies, where transistors are overstressed, resulting in high power consumption and low battery autonomy.
Innovation Solution
The use of even order harmonics, specifically the second-order harmonic, is introduced in the common-mode path of a power amplifier system to mitigate voltage stress on transistors, while maintaining low ON resistance and efficiency, by configuring an LC tank to resonate at fundamental and even-order harmonic frequencies and feeding these harmonics to the gates of the transistor stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are stacked to reduce voltage stress on individual devices, then transistor reliability is improved, but the ON resistance increases leading to higher power losses
Solution Approach 1:
The patent applies periodic action by introducing even-order harmonic signals at specific frequencies to the gates of stacked transistors. This periodic voltage modulation creates time-varying gate control that reduces the effective ON resistance during high-current periods, thereby reducing power losses while maintaining transistor reliability through voltage stress distribution
Solution Approach 2:
The patent changes the electrical parameters by injecting even-order harmonic frequencies (e.g., 2nd harmonic at 2x fundamental frequency) into the gate control signals. This parameter modification alters the transistor operating characteristics dynamically, reducing ON resistance during critical periods without increasing voltage stress on individual devices
2Reliability
If impedance matching network is used to reduce voltage stress on transistors, then transistor reliability is improved, but the network losses increase reducing efficiency
Solution Approach 1:
The patent extracts the voltage stress mitigation function from the traditional impedance matching network and implements it directly through harmonic injection at transistor gates. This removes the need for complex external matching networks that cause losses, while achieving the same reliability improvement through direct transistor control
3Reliability
If degeneration is applied to distribute voltage stress evenly across stacked transistors, then transistor reliability is improved, but the ON resistance increases reducing efficiency
Solution Approach 1:
The patent uses periodic even-order harmonic injection to dynamically adjust gate voltages during operation. This creates effective voltage distribution across stacked transistors similar to degeneration, but with time-varying control that reduces ON resistance during high-current periods, avoiding the continuous resistance penalty of static degeneration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces voltage stress on transistors, minimizing power losses and enhancing efficiency by maintaining high gate voltages during high current flow, thus achieving stable transistor characteristics and improved power amplifier performance.
Implementation Method 1
configuring an LC tank to resonate at fundamental and even-order harmonic frequencies and feeding these harmonics to the gates of the transistor stack
Data Source
AI summary
A power amplifier system includes a transistor stack and an upper portion. The upper portion includes an LC tank. The LC tank is configured to generate selected harmonics to mitigate voltage stress and facilitate amplifier efficiency. The transistor stack includes serial connected input transistors and upper transistors. The input transistors are configured to receive an input signal and the upper transistors are configured to provide an amplifier output signal. The LC tank is configured to provide the selected harmonics to at least gates of the upper transistors.