Vertically Stacked Anti-Fuse Cell Structure for Read Margin
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Solution Overview
Problem
The reliability and operation margin of traditional anti-fuses in semiconductor ICs are adversely affected by the down-scaling of transistors, particularly in FinFET and gate-all-around devices, and process changes at FEOL and MEOL impact their performance.
Innovation Solution
Implementing anti-fuses at metal layers above transistors with vertically stacked fuse elements having metal plates as terminals, allowing for higher read current and improved reliability through decoupled tuning of program voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If anti-fuses are implemented using transistors with breakdown path from gate to channel or drain, then the anti-fuse structure can be integrated with standard transistor fabrication, but the reliability and operation margin deteriorate due to down-scaling of transistors
Solution Approach 1:
The patent transitions the anti-fuse breakdown path from a lateral path within the transistor plane (gate to channel/drain) to a vertical path through stacked metal plates in the interconnect layers. This dimensional change moves the anti-fuse structure to a different spatial dimension (vertical stacking in metal layers above transistors), allowing integration with standard transistor fabrication while avoiding the reliability issues caused by transistor down-scaling.
2Productivity
If transistor geometry is scaled down to increase functional density, then production efficiency increases and costs decrease, but the reliability and operation margin of anti-fuses deteriorate
Solution Approach 1:
The patent relocates the anti-fuse structure from the transistor plane to vertical stacking in interconnect metal layers above the transistors. This allows continued scaling of transistor geometry for increased functional density and production efficiency, while the anti-fuse reliability is maintained through its separate vertical implementation path that does not depend on transistor dimensions.
Solution Approach 2:
The patent separates the anti-fuse function from the transistor structure by implementing anti-fuses as distinct stacked metal plate structures in interconnect layers. This segmentation allows independent optimization of transistor scaling for productivity while maintaining anti-fuse reliability through dedicated vertical stacking geometry.
3Reliability
If vertically stacked fuse elements with metal plates are implemented, then read current increases and reliability improves, but device complexity increases
Solution Approach 1:
The patent utilizes existing metal interconnect layers and stacking techniques from standard IC fabrication to implement the anti-fuse structure. The vertical stacking approach leverages established manufacturing capabilities for multi-layer metal interconnects, allowing the anti-fuse function to be added without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new fuse design provides higher read current and improved reliability with enhanced programmability, offering greater design flexibility and reduced cell size.
Implementation Method 1
the insulator breaks down and forms a low impedance path between the two metal plates
Data Source
AI summary
A method includes: forming a first transistor and a second transistor, each of the first transistor and the second transistor having a source terminal, a drain terminal, and a gate terminal; forming a word line conductor electrically connected to the gate terminal of the first transistor and the gate terminal of the second transistor; forming a program line conductor; and forming a vertically stacked dual anti-fuse element, including: forming a first metal plate, a second metal plate, and a third metal plate stacked over the first transistor and the second transistor and separated from each other by insulators; and electrically connecting the source terminal of the first transistor to the first metal plate, the source terminal of the second transistor to the third metal plate, and the program line conductor to the second metal plate.