Vertically Stacked Anti-Fuse Cell Structure for Scaled IC Reliability
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Solution Overview
Problem
As ICs scale down, traditional anti-fuses implemented using transistors face reliability and operation margin issues due to transistor scaling, and process changes at FEOL and MEOL affect their performance.
Innovation Solution
Implement anti-fuses at metal layers above transistors with vertically stacked fuse elements having metal plates as terminals, allowing for higher read current and improved reliability through decoupled tuning of program voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional anti-fuses implemented using transistors are used, then the structure is simple and manufacturing is established, but reliability and operation margin deteriorate due to transistor scaling
Solution Approach 1:
The patent transitions from planar transistor-based anti-fuses to vertically stacked metal plate anti-fuses. The fuse elements are arranged in vertical stacks with multiple metal plates separated by insulators, utilizing the third dimension (vertical stacking) to achieve higher reliability without increasing lateral footprint, thereby resolving the contradiction between reliability improvement and device complexity.
Solution Approach 2:
The patent employs composite structures combining multiple metal plates with insulating materials between them to form vertically stacked fuse elements. This composite approach creates a more reliable anti-fuse structure that is less susceptible to scaling effects compared to single-transistor implementations, while the modular nature of the composite structure manages complexity.
2Productivity
If transistor-based anti-fuses are used, then manufacturing process is established, but operation margin and resistance variation worsen with scaling
Solution Approach 1:
By moving to vertical stacking of metal plates, the patent achieves better operation margin and reduced resistance variation while maintaining manufacturing productivity. The vertical architecture allows for controlled formation processes that are compatible with existing semiconductor manufacturing, improving reliability without sacrificing production efficiency.
3Reliability
If anti-fuses are implemented at metal layers above transistors with vertically stacked fuse elements, then read current and reliability improve, but device complexity increases
Solution Approach 1:
The vertical stacking architecture allows multiple fuse elements to be compacted in the vertical direction, improving reliability through redundant paths and better electrical characteristics while minimizing lateral space usage. This dimensional transition resolves the complexity issue by efficiently utilizing the vertical dimension rather than expanding laterally.
Solution Approach 2:
The vertically stacked metal plate structure serves multiple functions: it provides reliable anti-fuse operation, enables compact integration, and allows for scalable implementation across different technology nodes. This multi-functionality justifies the increased structural complexity by delivering multiple benefits simultaneously.
4Productivity
If vertically stacked fuse elements with metal plates are used, then read current increases and design flexibility improves, but manufacturing complexity increases
Solution Approach 1:
The vertical stacking approach generates higher read current by creating multiple parallel current paths through the stacked metal plates, while the formation processes are integrated into existing metal layer fabrication sequences, managing manufacturing complexity through process integration rather than entirely new manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new anti-fuse design provides higher read current, improved reliability, and greater design flexibility with vertically stacked fuse cells, addressing the limitations of traditional anti-fuses in scaled-down ICs.
Implementation Method 1
the insulator between the metal plates has broken down
Data Source
AI summary
A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.