Stacked Dielectric Antifuse Layout for Compact IC Programming
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Solution Overview
Problem
Existing IC device programming technologies, such as metal fuses and gate oxide antifuses, require high voltages or currents, which can damage circuitry and are costly and complex, and consume significant area on the IC device, limiting manufacturing yield and customization efficiency.
Innovation Solution
The use of dielectric antifuse structures that degrade an interlayer dielectric material to establish an electrical connection between conductor structures, reducing the need for high programming voltages and currents, and minimizing the area required for programming circuitry, allowing for more functional circuitry and smaller IC devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal fuses or gate oxide antifuses are used for programming, then manufacturing yield and customization capabilities are improved, but high voltages or currents are required which can damage circuitry and increase device complexity
Solution Approach 1:
The patent changes the electrical parameters of the fuse structure by using a stacked configuration of first and second fuses with different orientations. This allows the programming operation to be performed at lower voltages and currents compared to traditional single-fuse designs, thereby reducing the risk of damage to surrounding circuitry while maintaining programming reliability
Solution Approach 2:
The patent divides a single fuse function into two separate fuse elements (first fuse and second fuse) that are stacked and oriented in different directions. This segmentation allows each fuse to handle a portion of the programming stress, enabling lower programming voltages and currents to be used while still achieving reliable programming, thus reducing device complexity and damage risk
2Reliability
If traditional fuse structures are used, then programming functionality is achieved, but significant area is consumed on the IC device
Solution Approach 1:
The patent implements a nested structure where the second fuse is positioned directly over the first fuse in a stacked configuration. This vertical nesting allows both fuse elements to occupy a compact footprint area, significantly reducing the space required for programming circuitry compared to traditional lateral fuse arrangements while maintaining full programming functionality
Solution Approach 2:
The patent transitions from a traditional lateral arrangement of fuse elements to a vertical stacked configuration. By utilizing the vertical dimension (stacking fuses in the z-direction rather than spreading them out in the x-y plane), the design achieves compact area occupancy while preserving programming functionality, thus reducing the area consumed on the IC device
3Manufacturing precision
If high programming voltages or currents are applied, then desired programming is achieved, but other circuitry on the IC device may be damaged
Solution Approach 1:
The patent modifies the electrical parameters required for programming by using the stacked fuse configuration. This structure enables the programming operation to be completed with lower voltages and currents than traditional fuse designs, thereby achieving the desired programming precision while minimizing the harmful effects of high voltage/current on surrounding sensitive circuitry
Solution Approach 2:
By dividing the programming function into two series-connected fuse elements with different orientations, the patent segments the electrical stress during programming. Each fuse element experiences reduced stress compared to a single fuse, allowing programming to be achieved with lower overall voltages and currents, thus preventing damage to other IC device circuitry while maintaining programming precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric antifuse structure reduces the size of programming circuitry, lowers the programming voltage and current requirements, and consumes less than 10% of the area of traditional fuse designs, enhancing manufacturing yield and customization capabilities while maintaining reliability and scalability.
Implementation Method 1
dielectric antifuse structures that degrade an interlayer dielectric material to establish an electrical connection between conductor structures
Data Source
AI summary
An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.