Stacked Backside Contact Spacers for Higher Semiconductor Yield
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Solution Overview
Problem
Conventional semiconductor production processes using a single non-stacked spacer layer for forming backside source/drain contact spacers result in strict margin requirements, leading to increased fabrication errors and reduced yield due to limited tolerance for variability.
Innovation Solution
Implementing a semiconductor structure with multiple, stacked inner spacers between a silicon layer and a nanosheet at the source/drain region, including a first and second inner spacer, a third and fourth inner spacer, and a T-shaped gate region formed by these spacers, which increases the margin sizes for forming backside source/drain contacts and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single non-stacked spacer layer is used to form backside source/drain contact spacers, then the structure is simple and manufacturing is easier, but the margin size for forming backside source/drain contacts is limited, leading to increased fabrication errors and reduced yield
Solution Approach 1:
The single spacer layer is segmented into multiple stacked spacer layers (first, second, third, and fourth spacer layers), each contributing to the overall margin size. This segmentation allows for increased tolerance in forming backside source/drain contacts while maintaining structural integrity and electrical performance.
Solution Approach 2:
The spacer structure transitions from a two-dimensional single layer to a three-dimensional stacked multi-layer configuration. This dimensional change increases the vertical margin size, providing greater tolerance for contact formation variations and improving manufacturing reliability.
2Manufacturing precision
If a single non-stacked spacer layer is used, then the fabrication process is simpler, but the tolerance for variability in forming backside source/drain contacts is limited, resulting in increased fabrication errors
Solution Approach 1:
The spacer structure is divided into multiple discrete layers that can be formed and controlled independently, allowing for precise control of margin sizes and improved contact formation precision while managing manufacturing complexity through modular fabrication processes.
3Reliability
If multiple stacked inner spacers are implemented, then the margin sizes for forming backside source/drain contacts are increased and fabrication errors are reduced, but the device complexity and number of fabrication steps increase
Solution Approach 1:
The spacer structure is segmented into multiple layers (first, second, third, and fourth spacer layers) that can be formed using sequential deposition and etching processes. This segmentation provides increased margin sizes for contact formation, improving yield while allowing for controlled complexity through standardized fabrication steps.
Solution Approach 2:
The multiple spacer layers are nested vertically, with each layer positioned on top of the previous layer. This nested configuration maximizes the use of vertical space to increase margin sizes without significantly expanding the lateral footprint, thereby improving reliability while controlling device complexity.
Data Source
AI summary
A semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first inner spacer and a second inner spacer disposed on a silicon layer, a third inner spacer disposed on the first inner spacer, a fourth inner spacer disposed on the second inner spacer, a gate region disposed on the silicon layer, and a source/drain region disposed on a backside source/drain contact, where an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and where the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.