Stacked Bandgap Reference Chip Layout for Stress-Stable Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional band gap reference circuits require multiple reference voltage generation sources, leading to complex wiring and increased semiconductor chip area, making them large and susceptible to stress fluctuations.
Innovation Solution
A semiconductor device configuration with a lead frame, a first semiconductor chip mounted face-up, and a second semiconductor chip mounted face-down with a smaller size, incorporating a bandgap element in the band gap reference circuit to alleviate stress fluctuations and provide a stable reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple reference voltage generation sources are distributed on the chip, then stress fluctuations are inhibited, but wiring becomes complicated and chip area increases
Solution Approach 1:
The invention divides the reference voltage generation function into two separate semiconductor chips: a first chip containing multiple reference voltage generation sources and a second chip containing the bandgap element. This segmentation allows the functional blocks to be physically separated, reducing wiring complexity on a single chip while maintaining the stress fluctuation resistance benefit of distributed sources through the stacked configuration.
Solution Approach 2:
The invention transitions from a planar distribution of multiple sources on a single chip to a vertical stacked configuration using three-dimensional integration. By stacking the first and second semiconductor chips vertically, the patent achieves spatial separation that reduces in-plane wiring complexity while maintaining close physical proximity for electrical connection, thus resolving the contradiction between stress resistance and wiring simplicity.
2Reliability
If multiple reference voltage generation sources are distributed on the chip, then stress fluctuations are inhibited, but chip area increases
Solution Approach 1:
By segmenting the reference voltage generation function across two separate chips, the invention reduces the area required on each individual chip. The first chip can be optimized for containing multiple sources in a compact arrangement, while the second chip contains only the essential bandgap element, overall reducing the total device footprint compared to distributing all elements on a single large chip.
Solution Approach 2:
The invention employs a stacked configuration where the second semiconductor chip is positioned above the first chip, creating a vertical nesting arrangement. This three-dimensional integration allows the functional blocks to be stacked rather than spread out, significantly reducing the overall chip area while maintaining the distributed source configuration for stress fluctuation resistance.
3Area of stationary object
If a compact configuration is used, then chip area is reduced, but stress fluctuations may increase
Solution Approach 1:
The invention uses vertical stacking to achieve compactness in the planar dimension while maintaining stress fluctuation resistance through the separated functional blocks. By moving to three-dimensional integration, the patent reduces chip area without compromising reliability, as the first and second chips remain physically distinct enough to experience different stress conditions.
Solution Approach 2:
By segmenting the reference voltage generation function into two separate chips, the invention ensures that the multiple reference voltage generation sources on the first chip and the bandgap element on the second chip can experience different stress conditions, maintaining stress fluctuation resistance even in a compact stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration results in a compact semiconductor device with reduced stress fluctuations and highly accurate, stable reference voltage output, minimizing the overall size and chip area while maintaining high accuracy and stability.
Implementation Method 1
a bandgap element including a positive-negative (PN) junction and included in a band gap reference circuit
Data Source
AI summary
A semiconductor device includes: a lead frame; a first semiconductor chip mounted face-up above the lead frame; and a second semiconductor chip mounted face-down above the first semiconductor chip. The second semiconductor chip has a chip size smaller than a chip size of the first semiconductor chip. The second semiconductor chip includes a bandgap element (an NPN transistor, an N-parallel NPN transistor) including a positive-negative (PN) junction and included in a band gap reference circuit.