Stacked BAW Resonator Structure for CMOS Integration
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Solution Overview
Problem
Existing bulk acoustic wave (BAW) resonators are produced as standalone, 2D devices, which are large in volume and area, difficult to integrate with CMOS, BiCMOS SiGe HBTs, and 3D devices, and require complex and costly 3D packaging with high alignment accuracy, leading to high producing costs and low integration.
Innovation Solution
A BAW resonator with a piezoelectric film array and electrode layers, integrated with CMOS processes, featuring vertical and horizontal cavities and electrode interconnections, allowing for a stacked structure that reduces package volume and increases integration, using CMOS-compatible materials and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standalone 2D BAW resonator structure is used, then device performance is maintained, but device area and volume are large
Solution Approach 1:
The patent transitions from a planar 2D resonator layout to a three-dimensional stacked structure by vertically stacking multiple resonator units (first resonator unit and second resonator unit) above and below the substrate. This vertical stacking enables multiple resonators to occupy the same footprint area, dramatically reducing the device area while maintaining individual resonator performance characteristics.
Solution Approach 2:
The resonator system is divided into multiple independent resonator units that can be stacked vertically. Each resonator unit contains separate piezoelectric films, electrodes, and cavity structures, allowing them to function independently while sharing the same substrate footprint. This segmentation enables high-density integration without compromising individual device performance.
2Adaptability or versatility
If 3D packaging technology is used to stack multiple 2D BAW resonators, then integration degree is improved, but producing cost and complexity increase
Solution Approach 1:
The patent merges the fabrication processes of multiple resonators into a single integrated CMOS-compatible manufacturing flow. Multiple resonator units are formed simultaneously on the same substrate using shared process steps including piezoelectric film deposition, electrode formation, and cavity etching, eliminating the need for separate 3D packaging processes and reducing production complexity.
Solution Approach 2:
The resonator design uses universal structural elements that can be replicated and stacked. The cavity structure, electrode configuration, and piezoelectric film arrangement are designed to be consistent across different resonator units, allowing standardized fabrication processes to produce multiple resonators with identical performance characteristics using the same tooling and process parameters.
3Length of stationary object
If 3D packaging with bonding and TSV technology is used, then package height is reduced, but alignment accuracy and producing cost requirements become extremely high
Solution Approach 1:
The resonator structures are pre-formed with integrated alignment features during the CMOS fabrication process. The substrate, piezoelectric films, and electrode patterns are precisely positioned before stacking, eliminating the need for post-fabrication alignment operations. This preliminary positioning ensures high alignment accuracy without requiring expensive precision bonding equipment or complex alignment procedures.
Solution Approach 2:
The patent introduces intermediate layers including buffer layers, adhesion layers, and dielectric layers that facilitate the stacking process. These intermediary structures provide mechanical support, thermal expansion compensation, and electrical isolation between stacked resonator units, reducing stress and misalignment issues that would otherwise require extremely high precision bonding.
4Reliability
If standalone BAW resonator production is used, then device performance is maintained, but producing cost increases
Solution Approach 1:
By stacking resonators vertically in the third dimension, the patent increases production throughput without requiring additional substrate area. Multiple resonators are fabricated simultaneously on a single substrate using the same CMOS process steps, effectively multiplying output per wafer and reducing the cost per device while maintaining performance specifications.
Solution Approach 2:
The patent utilizes CMOS-compatible materials and process parameters including silicon-based substrates, aluminum nitride or zinc oxide piezoelectric films, and standard metal electrodes. These parameter choices enable the use of existing high-volume CMOS manufacturing infrastructure, leveraging economies of scale to reduce production costs while maintaining resonator performance through controlled deposition thicknesses and pattern dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact, integrated BAW resonator with reduced interface resistance and cost, suitable for CMOS, BiCMOS SiGe HBTs, and 3D devices, improving integration and reducing complexity in manufacturing.
Implementation Method 1
a piezoelectric film array, including multiple piezoelectric films between a substrate of a chip and a capping layer on the top
Implementation Method 2
a contact region formed by ion implantation, which is located in the capping layer and is electrically connected to an electrode layer at the top surface of a top piezoelectric film
Data Source
AI summary
A BAW resonator includes: a piezoelectric film array, including multiple piezoelectric films between a substrate of a chip and a capping layer on the top, where multiple first cavities are provided between adjacent piezoelectric films in a vertical direction, between the piezoelectric films and the capping layer, and between the piezoelectric films and the substrate, second cavities are shared between adjacent piezoelectric films in a first direction in a horizontal plane, and third cavities are shared between adjacent piezoelectric films in a second direction in the horizontal plane; multiple electrode layers, covering at least the top surface and bottom surface of each of the piezoelectric films; and multiple electrode interconnection layers, connected to the electrode layers on the bottom surfaces of the piezoelectric films along sidewalls of the third cavities.