Stacked BGA Module with Interposer for Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microelectronic packaging methods do not efficiently utilize limited surface area on printed circuit boards, leading to reduced circuit density and increased signal lead lengths, which affects high clock speeds and parasitic inductance and capacitance.
Innovation Solution
A stacked microelectronic module comprising at least two IC package layers with an interposer layer for electrical signal rerouting and angularly depending leads for interconnection to an interface PCB, allowing for efficient stacking and interconnection of ball grid array packages, thereby reducing signal lead lengths and enhancing circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar packaging is used, then PCB surface area utilization is poor, but circuit density is reduced and signal lead lengths are increased
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional stacked packaging, arranging multiple IC packages vertically along the Z-axis. This dimensional change enables efficient utilization of PCB surface area while significantly increasing circuit density, as multiple functional layers can coexist within the same footprint without increasing lead lengths
2Area of stationary object
If traditional planar packaging is used, then PCB surface area utilization is poor, but signal lead lengths are increased causing increased parasitic inductance and capacitance
Solution Approach 1:
By stacking IC packages vertically in three dimensions, the patent minimizes horizontal signal travel distances. Signals traverse shorter paths through vertical interconnections rather than long planar routes, thereby reducing parasitic inductance and capacitance while improving PCB space utilization
3Productivity
If stacked IC packages are implemented, then circuit density is increased and signal lead lengths are reduced, but device complexity is increased
Solution Approach 1:
The patent introduces an interposer layer as an intermediary component between stacked IC packages. This interposer provides standardized interconnection interfaces, simplifies alignment, and manages complex signal routing, thereby enabling high circuit density while controlling overall device complexity through modular architecture
4Object-affected harmful factors
If stacked IC packages are implemented, then parasitic inductance and capacitance are reduced, but manufacturing complexity is increased
Solution Approach 1:
The patent employs preliminary alignment features and pre-configured interposer layers that establish registration marks and guide structures before final assembly. This preliminary preparation simplifies the stacking process, enables automated assembly, and reduces manufacturing complexity despite the advanced three-dimensional architecture
Data Source
AI summary
A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.