Stacked Bipolar Transistor Architecture for High-Power RF Amplifiers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon-based integrated circuit technologies face limitations in RF output power, which hinders their use in millimeter-wave communications, despite advancements in frequency and speed, due to reduced breakdown voltage and increased complexity in impedance matching when transistors are scaled for higher speed.
Innovation Solution
The implementation of a High Voltage/High Power (HiVP) amplifier architecture using stacked Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs), which allows for high bias voltages, increased RF output voltage swings, and simplified impedance matching by providing a single bias source for all transistors in the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors are scaled down to increase fT/fMAX for higher speed operation, then the frequency of unity gain and maximum frequency of operation are improved, but the breakdown voltage is reduced
Solution Approach 1:
The patent divides a single high-voltage transistor into multiple stacked transistors, each operating at lower individual voltages. The stacked configuration segments the total voltage across multiple devices, allowing the system to achieve high breakdown voltage capability while maintaining the small, fast transistor geometry needed for high fT/fMAX operation.
2Speed
If transistors are scaled down to increase fT/fMAX, then the speed is improved, but the RF output power is reduced
Solution Approach 1:
The patent combines multiple stacked transistors in parallel to achieve power combining. Each transistor operates at high speed with its own optimized geometry, and their outputs are combined to deliver high RF output power. This merging approach allows the system to benefit from both the high-speed characteristics of scaled transistors and the high power output of larger devices.
3Speed
If transistors are scaled down for higher speed, then the carrier transit time is reduced, but the output impedance becomes more difficult to match
Solution Approach 1:
The stacked transistor configuration serves multiple functions simultaneously: it provides high breakdown voltage, maintains high-speed operation, and presents a controlled output impedance that is more amenable to standard impedance matching techniques. The stack architecture creates a more universal solution that addresses multiple performance requirements with a single configuration.
4Ease of manufacture
If silicon-based technology is used instead of III-V technology, then the production cost is reduced, but the RF output power capability is reduced
Solution Approach 1:
The patent changes the operating parameters of silicon-based transistors by stacking them in a configuration that enables high-voltage operation. This parameter change allows silicon devices to achieve RF output power levels previously only attainable with III-V technologies, while maintaining the cost advantages of silicon manufacturing processes.
Data Source
AI summary
An amplifier for an integrated circuit has a plurality of ratioed current mirrors connected to each other in a stacked configuration. Each ratio mirror has at least two resistors and at least two bipolar transistors connected to each other via said at least two resistors. Each amplifying transistor, contains a capacitor, and potentially and inductor, to internally match the transistors that make up the amplifying stack. DC, harmonic and s-parameter simulations are performed to provide an optimal impedance for each of the stacked transistors to maximize the RF power output of each stacked layer and the amplifier.