Memory Array Bit Line Stacking for Lower Resistance Paths
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in reducing the resistance of conductive lines within digital devices, which affects operating voltages and overall IC performance as ICs become smaller and more complex.
Innovation Solution
The use of bit lines on multiple conductive layers, specifically a first conductor in a first conductive layer and a second conductor in a second conductive layer, electrically coupled by vias, reduces the resistance of the bit line, allowing for a longer bit line length and a larger array of memory cells compared to other approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are implemented using a single conductive layer, then the device complexity is reduced, but the resistance of the bit line increases
Solution Approach 1:
The patent transitions from a single-plane conductive structure to a multi-layer three-dimensional structure. Bit lines are formed using multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) stacked vertically and connected via vias. This dimensional change allows the bit line to achieve lower resistance through increased effective cross-sectional area while maintaining a compact footprint, resolving the contradiction between structural simplicity and electrical performance.
2Length of moving object
If bit line resistance is reduced by using multiple conductive layers, then the bit line length can be increased, but the device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of conductive layers to extend the effective bit line length without proportionally increasing the lateral footprint. Multiple conductive layers connected by vias create parallel current paths, effectively increasing the conductive length and reducing resistance while maintaining a compact two-dimensional area, thus enabling longer bit lines with controlled complexity.
Solution Approach 2:
The patent merges multiple conductive layers into a unified bit line structure. The first, second, and third conductive layers are electrically connected through vias to form a single continuous bit line that spans multiple memory cell columns. This merging of layers creates an equivalent parallel conductor system that reduces overall resistance while achieving extended bit line length across the memory array.
3Quantity of substance
If the array size is increased to improve memory capacity, then more memory cells are included, but the bit line resistance increases
Solution Approach 1:
The patent addresses the resistance increase in large-scale memory arrays by implementing a multi-layer conductive structure. As the array size expands to include more memory cells, the bit line traverses longer distances and more columns. The stacked conductive layers with via connections provide multiple parallel conduction paths, reducing the overall resistance despite the increased length required to span the larger array, thereby enabling high-capacity memory implementation.
Data Source
AI summary
A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.