Stacked Ferroelectric Bit-Cell Capacitors for Dense Low-Power Memory
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM and flash memories, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption, and traditional ferroelectric memories suffer from charge degradation and disturbance issues.
Innovation Solution
The use of stacked and folded capacitor configurations in memory bit-cells, combined with word-line boosting and refresh mechanisms, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce area occupancy and improve power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple capacitors are used in memory bit-cells, then memory density and endurance are improved, but area occupancy increases
Solution Approach 1:
The patent implements stacked capacitor structures where capacitors are vertically nested above each other, sharing common bottom electrodes and interconnect structures. This nesting approach allows multiple capacitors to occupy a reduced horizontal footprint while maintaining individual capacitor functionality and capacity, directly resolving the contradiction between improved memory endurance (requiring multiple capacitors) and reduced area occupancy.
Solution Approach 2:
The patent transitions from planar capacitor arrangements to three-dimensional stacked configurations, utilizing the vertical dimension to accommodate multiple capacitors. By stacking capacitors vertically and sharing common electrodes, the design achieves higher capacitor density without proportionally increasing the horizontal area, thereby improving memory endurance while controlling area occupancy.
2Duration of action of stationary object
If conventional non-volatile memories are used, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent employs ferroelectric materials with specific phase transitions and hysteresis characteristics to achieve non-volatile data retention at lower operating voltages. By utilizing the ferroelectric effect and carefully controlling material composition and thickness, the design maintains data retention capabilities while reducing the energy required for write and read operations compared to conventional non-volatile memories.
Solution Approach 2:
The patent uses composite ferroelectric capacitor structures combining multiple material layers with different functional properties. These composite materials provide both non-volatile data retention through ferroelectric polarization and reduced power consumption through optimized switching characteristics and lower operating voltages, resolving the contradiction between data retention and power consumption.
3Area of stationary object
If capacitor dimensions are reduced, then area occupancy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the capacitor structure into modular segments with standardized layer thicknesses and electrode patterns. This segmentation approach allows for scalable manufacturing where each layer can be deposited and patterned using standard fabrication processes, reducing the impact of dimensional reductions on overall manufacturing precision requirements while maintaining small capacitor footprints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces charge disturbance, enhances memory endurance, and optimizes area usage, making non-volatile memories more suitable for low-power and compact devices by minimizing power consumption and improving memory density.
Implementation Method 1
A first capacitor of the plurality of capacitors includes a first ferroelectric dielectric material
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.