Stacked Nano-Layer BJTs and Diodes for Thinned Substrates
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Solution Overview
Problem
Existing integrated circuit devices face challenges in forming bipolar junction transistors (BJTs) and P-N junction diodes on thinned substrates with backside power delivery networks, as the substrate thickness is insufficient to accommodate these components, and current fabrication processes are complex and inefficient.
Innovation Solution
The integration of BJT and P-N junction diodes on the surface of the substrate, rather than within it, using nano-semiconductor layers and vertical semiconductor layers with conductive contacts, allowing for concurrent formation with stacked FETs using simplified fabrication processes, even on thinned substrates with backside power delivery networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BJTs and P-N junction diodes are formed within the substrate, then device integration is achieved, but substrate thickness must be sufficient which conflicts with thinned substrate requirements for BSPDN
Solution Approach 1:
The patent transitions from forming BJT and P-N junction diodes within the substrate (3D embedding) to forming them on the substrate surface (2D planar arrangement). This dimensional change allows the devices to be constructed using stacked nano-semiconductor layers and vertical semiconductor layers that extend upward from the substrate surface, eliminating the need for thick substrates while maintaining device functionality and enabling BSPDN integration on the substrate backside.
Solution Approach 2:
The BJT and P-N junction diode structures are segmented into multiple discrete nano-semiconductor layers stacked vertically, with each layer serving a specific functional region (emitter, base, collector for BJT; anode, cathode for diode). This segmentation allows the devices to be constructed in a layered fashion on the substrate surface rather than requiring continuous 3D formation within the substrate bulk.
2Productivity
If stacked nano-semiconductor layers are used to form BJT and P-N junction diodes on substrate surface, then integration density increases and fabrication is simplified, but additional vertical structure complexity is introduced
Solution Approach 1:
The patent merges the formation of BJT and P-N junction diodes with the existing stacked FET fabrication process. The same alternating semiconductor layers are used to form all device types, and the vertical semiconductor layers serve multiple functions by contacting different regions of the stacked layers. This merging approach increases integration density while avoiding significant increases in fabrication process complexity.
Solution Approach 2:
The vertical semiconductor layers serve multiple functions: they form the base region for BJT, provide contact regions for P-N junction diodes, and enable electrical connections between different stacked layers. This multi-functionality reduces the need for separate specialized structures for each device type, simplifying the overall fabrication process while maintaining high integration density.
Data Source
AI summary
Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.