Stacked Semiconductor Bonding Layout for Alignment and Arc Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in enhancing capacity and reliability when multiple semiconductor structures are stacked vertically and electrically connected, particularly in maintaining proper alignment and preventing defects such as arcing during the etching process for forming through electrodes.
Innovation Solution
The semiconductor device design includes a lower and upper semiconductor structure with specific regions and bonding pads, along with dummy conductive patterns and through electrodes, allowing for hybrid bonding and Daisy chain connections, which ensures proper alignment and prevents defects by providing alternative paths for charge dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor structures are stacked vertically to increase capacity, then device capacity is improved, but alignment precision and reliability deteriorate due to increased complexity and potential defects
Solution Approach 1:
The patent introduces alignment marks and dummy patterns before the main bonding process to establish precise registration between stacked semiconductor structures. These preliminary features guide subsequent alignment operations, ensuring accurate positioning despite the increased complexity of multi-structure stacking.
Solution Approach 2:
The patent employs dummy conductive patterns and alignment mark structures as intermediary elements that facilitate precise alignment between bonding pads of different semiconductor structures. These intermediary features serve as reference points that mediate the alignment process, enabling accurate positioning without directly involving the functional bonding pads.
2Adaptability or versatility
If through electrodes are formed by etching semiconductor substrates to enable electrical connections, then device functionality is improved, but harmful effects such as arcing occur during the etching process
Solution Approach 1:
The patent converts the harmful arcing phenomenon during etching into a beneficial self-aligned etching process. By utilizing the arc discharge between electrodes, the method achieves precise etching of through-holes while the arc path itself defines the etching boundary, transforming the harmful effect into a useful alignment mechanism.
Solution Approach 2:
The patent replaces conventional mechanical or photochemical etching methods with an electrical discharge (arc) etching process. This substitution allows for direct, self-aligned formation of through-holes through controlled arc discharge, eliminating the need for complex masking and multi-step etching procedures while reducing harmful side effects.
3Device complexity
If bonding pads are directly connected between stacked structures to simplify connections, then device complexity is reduced, but reliability deteriorates due to lack of alternative paths for charge dissipation
Solution Approach 1:
The patent introduces dummy conductive patterns in non-critical regions of the semiconductor structure. These dummy patterns provide localized alternative paths for charge dissipation without affecting the primary functional connections. By placing conductive elements strategically in areas where they won't interfere with main signal paths, the system gains redundancy while maintaining simplicity.
Solution Approach 2:
The patent modifies the electrical parameters of the semiconductor structure by adding dummy conductive patterns that change the charge distribution and dissipation pathways. This parameter change provides alternative routes for charge flow, improving reliability without adding complex connection structures, as the dummy patterns are electrically passive but functionally beneficial.
Data Source
AI summary
A semiconductor device may include: a lower semiconductor structure including a lower semiconductor substrate including a first region and a second region, a lower circuit structure disposed in the first region over the lower semiconductor substrate, a lower bonding pad disposed over the lower circuit structure and connected thereto, and a dummy conductive pattern disposed in the second region over the lower semiconductor substrate; an upper semiconductor structure including an upper semiconductor substrate disposed over the lower semiconductor structure and including the first region and the second region, an upper circuit structure disposed in the first region under the upper semiconductor substrate, and an upper bonding pad disposed under the upper circuit structure and connected thereto while being bonded to the lower bonding pad; a through electrode; and a dummy through electrode passing through the upper semiconductor structure and connected to the dummy conductive pattern.