Stacked Bonding Pad Layout for Warpage-Tolerant Semiconductor Interconnects
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices by bonding three or more substrates via interlayer dielectrics lies in effectively forming bonding pads that maintain electrical connectivity while preventing high resistance and disconnection due to shape mismatches and wafer warpage during the bonding process.
Innovation Solution
The semiconductor device design incorporates metal pads with different shapes and sizes on each substrate, specifically setting small areas for pads on one substrate and larger areas on another to enhance integration and prevent disconnection, while using specific insulating materials like SiCN and SiO2 to control copper diffusion and prevent misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal pads with the same shape and size are used on all substrates, then the manufacturing process is simple, but misalignment and disconnection occur due to wafer warpage during bonding
Solution Approach 1:
The patent applies asymmetry by configuring metal pads with different shapes and sizes on different substrates. Specifically, pads on the first substrate have a first shape while pads on the second substrate have a second shape that is different from the first shape. This asymmetric design compensates for misalignment caused by wafer warpage during bonding, ensuring reliable electrical connectivity despite the complexity introduced in pad formation.
2Reliability
If metal pads with different shapes and sizes are used on substrates, then misalignment is prevented and connectivity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by making each metal pad's shape and size specific to its location and function on the substrate. Pads are configured with different shapes (e.g., rectangular, square, circular) and sizes according to their specific requirements. This localized customization ensures optimal electrical connectivity for each pad while managing the overall manufacturing complexity through systematic design.
3Ease of manufacture
If copper diffusion is not controlled, then the manufacturing process is simpler, but high resistance and disconnection occur at bonding interfaces
Solution Approach 1:
The patent applies the intermediary principle by introducing a barrier layer between the metal pads and interlayer dielectric materials. This barrier layer acts as a mediator that prevents copper diffusion from the metal pads into the dielectric materials, thereby maintaining electrical conductivity and preventing high resistance or disconnection at bonding interfaces. The barrier layer is formed through specific material selection and deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the integration density of metal pads, reduces the risk of high resistance and disconnection, and effectively prevents copper atom diffusion, ensuring reliable electrical connectivity across bonding interfaces.
Implementation Method 1
a first insulator layer and a second insulator layer which are different from each other are formed on the first substrate in this order
Implementation Method 2
In a case where a semiconductor device is manufactured by bonding three or more substrates via inter layer dielectrics
Data Source
AI summary
In one embodiment, a semiconductor device includes a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, disposed on the first pad, and being in contact with the first pad. The device further includes a third pad provided in the second insulator, and disposed above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, disposed on the third pad, and being in contact with the third pad. Furthermore, a shape of the third or fourth pad is different from a shape of the first or second pad.