Stacked Bootstrap Capacitors for DC/DC Converter Efficiency
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Solution Overview
Problem
Existing DC/DC boost converters require large capacitors for stable bootstrap voltage, leading to area costs and additional switching losses that reduce converter efficiency.
Innovation Solution
The use of stacked bootstrap capacitors that can be charged to different voltages, reducing the area required and improving efficiency by sharing charge between capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large capacitor is used to create a stable bootstrap voltage, then the bootstrap voltage stability is improved, but the chip area occupied increases and switching losses increase
Solution Approach 1:
The single large bootstrap capacitor is divided into multiple smaller capacitors (first bootstrap capacitor and second bootstrap capacitor) connected in parallel. This segmentation maintains the total capacitance value needed for stable bootstrap voltage while reducing the peak current demand during switching transitions, thereby lowering switching losses and allowing for more efficient area utilization on the chip.
2Reliability
If a large capacitor is used to create a stable bootstrap voltage, then the bootstrap voltage stability is improved, but the switching losses increase
Solution Approach 1:
By dividing the total capacitance into multiple smaller capacitors, the instantaneous current requirements during switching events are distributed. This reduces the peak current stress on the switching transistors and minimizes the energy lost during switching transitions, while still providing the necessary total capacitance for bootstrap voltage stability.
3Area of stationary object
If stacked bootstrap capacitors are used, then the chip area is reduced, but the circuit complexity increases
Solution Approach 1:
The first and second bootstrap capacitors are connected in parallel configuration, merging their capacitance values to achieve the required total capacitance. This combining approach allows for area-efficient design while maintaining electrical simplicity, as the parallel connection naturally provides voltage equality and automatic charge distribution without requiring additional control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area needed for capacitors on the IC chip and enhances converter efficiency by minimizing switching losses and dynamic on-resistance.
Implementation Method 1
a first bootstrap capacitor having a first terminal coupled to a first node between the first switch and the second switch and a second terminal coupled to a second node between the fourth switch and the fifth switch; and a second bootstrap capacitor having a first terminal coupled to the first node and a second terminal coupled to a third node between the sixth switch and the seventh switch
Data Source
AI summary
A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.