Vertically Stacked Bridge Dies for High-Bandwidth IC Packaging
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Solution Overview
Problem
Current Multi-Chip Module (MCM) packaging architectures are limited in scaling to higher bandwidth and signal speeds due to bandwidth reduction, signal delay, and signal distortion, primarily because IC dies are stacked parallel to each other, restricting the placement of high-power compute IC dies and hindering efficient heat dissipation.
Innovation Solution
The proposed solution involves coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds, allowing for a metallization stack with conductive traces parallel to one surface and orthogonal to the other, enabling more efficient electrical and thermal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC dies are stacked parallel to each other in conventional MCM packaging, then the packaging structure is simple and easy to manufacture, but the bandwidth is reduced and signal delay increases
Solution Approach 1:
The patent transitions from conventional parallel stacking of IC dies to a vertical stacking architecture where dies are arranged in the third dimension (height). This dimensional change enables shorter signal paths between dies, reducing signal delay and improving bandwidth while maintaining manufacturing feasibility through adapted interconnect structures.
Solution Approach 2:
The patent implements nested interconnect structures where multiple conductive layers and interconnect paths are integrated within the vertical stack. The interconnect architecture nests signal pathways through intermediate dies and substrate layers, enabling complex signal routing while maintaining compact vertical form factor.
2Quantity of substance
If high-power compute IC dies are placed in conventional parallel stacking, then device density is limited, but heat dissipation becomes more difficult
Solution Approach 1:
The vertical stacking architecture redistributes heat-generating components across multiple vertical layers rather than concentrating them in a single plane. This dimensional redistribution increases device density while improving thermal management by creating graduated heat paths from upper to lower dies and substrate.
Solution Approach 2:
The patent introduces intermediate dies and substrate structures that act as thermal mediators. These intermediate layers provide thermal pathways and heat sinking capabilities between high-power compute dies, facilitating heat dissipation while maintaining high device density in the vertical stack.
3Reliability
If vertically stacked bridge dies with planarized edges are used, then electrical connectivity and thermal management are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies planarization processes to bridge die edges before stacking to pre-establish flat bonding surfaces. This preliminary action ensures proper alignment and contact between vertically stacked dies, enhancing electrical connectivity while managing manufacturing complexity through process sequencing.
Solution Approach 2:
The bridge dies in the patent serve multiple functions: they provide mechanical support for vertical stacking, establish electrical interconnects between compute dies, and facilitate thermal management pathways. This multi-functionality reduces the need for separate specialized components, balancing enhanced connectivity with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical connectivity and thermal management, allowing for increased density of high-power compute IC dies and improved performance in next-generation servers by reducing thermal stress and increasing conductive pathways.
Implementation Method 1
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 2
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 3
allowing for a metallization stack with conductive traces parallel to one surface and orthogonal to the other, enabling more efficient electrical and thermal connectivity
Implementation Method 4
enhances electrical connectivity and thermal management, allowing for increased density of high-power compute IC dies and improved performance in next-generation servers by reducing thermal stress and increasing conductive pathways
Data Source
AI summary
Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.