Stacked Bridge Semiconductor Package for Higher On-Package Capacitance
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Solution Overview
Problem
Semiconductor packages face challenges in miniaturization and cost reduction while maintaining high-capacity data processing, as the limited area of traditional bridges restricts the capacity of capacitors within the package.
Innovation Solution
A semiconductor package design featuring a substrate with a cavity, stacked bridge chip structures, and vertical connection layers, which includes capacitors such as metal-insulator-metal (MIM), deep trench, or integrated stack capacitors, and through silicon vias (TSVs) to connect regions with different voltage levels, enhancing power integrity and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a traditional bridge structure is used in the package substrate, then the package achieves miniaturization and cost reduction, but the capacitor capacity is limited due to the small bridge area
Solution Approach 1:
The patent transitions from a two-dimensional planar bridge structure to a three-dimensional stacked configuration by placing multiple bridge chips vertically on top of each other. This vertical stacking enables the capacitor structure to extend in the height dimension, significantly increasing the effective capacitor area and capacity without expanding the lateral footprint of the package.
Solution Approach 2:
The patent implements a nested structure where the second bridge chip is positioned directly on top of the first bridge chip, and the capacitor structure is integrated within and around these stacked bridge chips. This nesting approach maximizes the use of vertical space, allowing the capacitor to occupy the three-dimensional volume defined by the stacked bridges, thereby increasing capacity without increasing package area.
2Quantity of substance
If the bridge area is increased to accommodate larger capacitors, then capacitor capacity improves, but the package size increases contrary to miniaturization goals
Solution Approach 1:
Instead of increasing capacitor capacity by expanding the lateral area of the bridge, the patent utilizes the vertical dimension by stacking bridge chips and integrating the capacitor structure in the height direction. This approach increases capacitor capacity while maintaining a compact lateral footprint, thus achieving miniaturization.
Solution Approach 2:
The patent incorporates the capacitor structure within the bridge chip stack during the manufacturing process, rather than adding it as a separate external component. This integration approach eliminates the need for additional package volume that would be required for external capacitors, thereby maintaining miniaturization while providing sufficient capacitance.
3Quantity of substance
If multiple bridge chips are stacked to increase capacitor capacity, then capacitor capacity and power integrity improve, but the device complexity increases
Solution Approach 1:
The patent combines multiple functions into the stacked bridge chip structure: the bridges provide both interconnect functionality between heterogeneous dies and serve as the structural foundation for the capacitor. The capacitor electrodes are formed using the same conductive layers and materials as the bridge interconnects, eliminating the need for separate capacitor components and reducing overall device complexity.
Solution Approach 2:
The stacked bridge chip structure serves multiple purposes simultaneously: it provides electrical interconnection between different dies, establishes vertical stacking for three-dimensional integration, and forms the electrode structure for the capacitor. This multi-functionality reduces the number of separate components needed, thereby managing device complexity despite the increased stacking.
Data Source
AI summary
A semiconductor package includes a substrate having a cavity, a bridge chip structure in the cavity of the substrate and including a first bridge chip and a second bridge chip stacked on the first bridge chip, and a plurality of semiconductor chips spaced apart laterally on the substrate. Each of the plurality of semiconductor chips includes a first region that is electrically connected to the first bridge chip and a second region that is electrically connected to the second bridge chip.