Stacked BSI Image Sensor Layout for Photonic-Electrical Tradeoffs
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Solution Overview
Problem
Existing CMOS image sensors face a trade-off between photonic performance and electrical performance due to the need to form photo diodes and transistors on different chips, which limits overall sensor efficiency.
Innovation Solution
A vertically integrated backside illuminated (BSI) image sensor is developed, comprising three chips: one with photo-sensitive elements, another with pixel transistors, and a third with logic circuits, allowing independent manufacturing and operation of these components using different technology nodes, thereby improving both photonic and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If photo diodes and transistors are formed on different chips, then manufacturing flexibility is improved, but device complexity increases
Solution Approach 1:
The image sensor is divided into multiple separate chips: a first chip containing photo diodes and a second chip containing transistors. These chips are formed using different technology nodes and then bonded together, allowing independent optimization of photonic and electrical performance while maintaining manufacturing flexibility.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by bonding the first chip (photo diodes) to the second chip (transistors) in a vertical configuration. This dimensional change enables independent manufacturing of each chip layer while achieving functional integration.
2Device complexity
If photo diodes and transistors are integrated on the same chip, then device complexity is reduced, but photonic performance deteriorates
Solution Approach 1:
The image sensor is divided into multiple separate chips: a first chip containing photo diodes and a second chip containing transistors. These chips are formed using different technology nodes and then bonded together, allowing independent optimization of photonic and electrical performance while maintaining manufacturing flexibility.
3Reliability
If advanced logic circuits are implemented, then electrical performance is improved, but power consumption increases
Solution Approach 1:
The patent implements advanced logic circuits with optimized power characteristics by forming them on a separate third chip using specific technology nodes. This allows independent optimization of logic circuit performance and power consumption through parameter control in the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances quantum efficiency and reduces power consumption by optimizing chip area utilization and enabling advanced logic circuits, while maintaining high performance.
Implementation Method 1
a first chip including a plurality of photo-sensitive devices formed over a first semiconductor substrate
Data Source
AI summary
A semiconductor device includes a first chip including an array of photo-sensitive devices. The semiconductor device further includes a second chip bonded to the first chip. The second chip includes an array of pixel units. In some embodiments, at least one pixel unit of the array of pixel units includes a photo diode including. The photo diode includes an anode coupled to an electrical ground. The photo diode further includes a cathode coupled to a source of a transfer gate transistor. The second chip further includes a plurality of input/output transistors disposed along at least one edge of the array of pixel units.