Stacked IC Package Using C4 and Wirebond Interconnects
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Solution Overview
Problem
The existing packaging of integrated circuits (ICs) faces challenges in optimizing input/output (I/O) performance and minimizing production costs, particularly as the number of terminals increases, leading to longer interconnect lines that degrade performance due to increased resistance and parasitics.
Innovation Solution
The use of two or more different connection technologies, such as controlled-collapse chip connection (C4) and wirebonding, to stack and couple IC dice with a substrate, optimizing I/O bandwidth and reducing production costs by varying connector sizes and embedding ICs within the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of terminals that must be connected increases on each die, then the routing capability is improved, but the lengths of the interconnects increase leading to degraded I/O performance
Solution Approach 1:
The patent transitions from a planar interconnect architecture to a three-dimensional stacked architecture. By stacking multiple dies vertically with interconnect layers between them, the patent enables routing of multiple terminals without increasing the lateral length of interconnect lines. This vertical dimension allows high-density terminal connections while maintaining short interconnect paths, thus improving routing capability without degrading I/O performance.
2Adaptability or versatility
If the lengths of the interconnect lines are increased, then more terminals can be routed, but there is greater likelihood that I/O performance will be degraded by interconnect parasitics and increased resistance
Solution Approach 1:
The patent uses vertical stacking to provide multiple routing layers in the Z-dimension, allowing terminals to be connected through short vertical and lateral paths rather than long lateral routes. This reduces interconnect length and associated parasitics while enabling comprehensive terminal connectivity.
Solution Approach 2:
The patent divides the interconnect function across multiple separate interconnect layers between stacked dies. Each layer handles specific routing tasks, allowing optimization of each segment's length and reducing the total path length compared to a single-layer approach. This segmentation enables efficient signal routing with minimized parasitic effects.
3Ease of manufacture
If traditional single connection technology is used to stack IC dice, then manufacturing simplicity is maintained, but production costs increase and performance optimization is limited
Solution Approach 1:
The patent combines multiple connection technologies (solder bump and wirebond) within a single stacked die package. This merging allows each technology to be used where it provides the most benefit: solder bumps for robust electrical and mechanical connection, and wirebonds for flexible routing and signal transmission. The combination achieves better overall performance and cost efficiency while maintaining manufacturing feasibility through established processes.
Solution Approach 2:
The patent applies different connection technologies at different locations within the stack based on local requirements. Solder bumps are used at interfaces requiring robust mechanical and electrical connection, while wirebonds are used where flexible routing or space constraints exist. This localized optimization improves overall package performance and reduces production costs by using each technology where it provides the most value.
Data Source
AI summary
An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.