Stacked Cache Die Cooling Channels for Thermal Bottlenecks
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Solution Overview
Problem
Die stacking in integrated circuits poses thermal management challenges due to inefficient heat dissipation.
Innovation Solution
A stacked assembly with a dielectric encasing a semiconductor die that includes a cooling channel with inlets and outlets, configured to direct cooling fluid to the die, utilizing UV-transparent material for sacrificial layer removal and dielectric layer deposition to form enclosed channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If die stacking is used to enhance packaging density, then packaging density is improved, but thermal management becomes problematic due to inefficient heat dissipation
Solution Approach 1:
The patent segments the thermal management system by introducing separate cooling channels within the dielectric material that can independently direct cooling fluid to different regions of the stacked dies. This segmentation allows targeted heat dissipation from each die, resolving the thermal management problem while maintaining the high packaging density achieved through stacking.
Solution Approach 2:
The patent introduces a dielectric material with embedded cooling channels as an intermediary between the stacked dies and the cooling fluid. This intermediary structure enables efficient heat transfer from the dies to the cooling fluid while maintaining electrical insulation, thus improving heat dissipation efficiency without compromising packaging density.
2Temperature
If cooling channels are added to the dielectric encasing, then thermal performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the cooling channel structure with the dielectric encasing material, creating an integrated component rather than separate additions. The cooling channels are formed within the dielectric material itself, combining the structural and thermal management functions into a single element, thus improving thermal performance without proportionally increasing device complexity.
Solution Approach 2:
The dielectric material serves multiple functions: it provides electrical insulation, structural support, and thermal management through embedded cooling channels. This multi-functionality reduces the need for separate components, thereby improving thermal performance while minimizing the increase in device complexity.
3Manufacturing precision
If sacrificial layer removal and dielectric deposition steps are added, then manufacturing precision is improved, but ease of manufacture decreases
Solution Approach 1:
The patent employs preliminary action by depositing a sacrificial layer before forming the cooling channels, and then removing it to create precise channel structures. This preliminary preparation enables accurate channel formation and subsequent dielectric deposition, improving manufacturing precision through controlled sequential steps.
Solution Approach 2:
The patent replaces traditional mechanical drilling or etching methods with a chemical sacrificial layer removal process followed by dielectric deposition. This substitution allows for more precise channel formation and better integration with the surrounding dielectric material, improving manufacturing precision despite the additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances thermal performance by reducing die temperatures, with simulated reductions from 130°C to 70°C for the top die and 65°C for the bottom die using 20 μm channels with cooling fluid at 20°C.
Implementation Method 1
applying ultraviolet radiation to the sacrificial layer through the layer of ultraviolet-transparent material to cause gasification and removal of the sacrificial material
Implementation Method 2
The cooling channel is configured to direct cooling fluid to at least the second semiconductor die
Data Source
AI summary
A stacked assembly includes a first semiconductor die; a second semiconductor die secured to the first semiconductor die; and a dielectric encasing at least the second semiconductor die. The dielectric defines a cooling channel having at least one inlet and at least one outlet, and the cooling channel is configured to direct cooling fluid to at least the second semiconductor die.