3D Stacked Cache Memory Thermal Management via Selective Operation
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Solution Overview
Problem
In three-dimensional stacked die arithmetic devices, the cache memory can become inoperable due to heat generation by the arithmetic unit, limiting the number of cores and cache memories that can be stacked and hindering computing power and memory capacity improvements.
Innovation Solution
A cache memory equipped arithmetic device is designed with a first semiconductor die containing multiple arithmetic circuits and a second semiconductor die stacked over the first, containing multiple cache memories. These components form pairs where the arithmetic circuit and cache memory at least partially overlap, and an operation management circuit selectively operates either the arithmetic circuit or the cache memory based on the needed arithmetic intensity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arithmetic units and cache memories are stacked in a three-dimensional structure to increase computing power and memory capacity, then the number of cores and cache memories can be increased, but the cache memory may become inoperable due to heat generation by the arithmetic unit
Solution Approach 1:
The patent divides the stacked die structure into separate arithmetic unit dies and cache memory dies, with each die containing multiple independent arithmetic units or cache memories. This segmentation allows for independent thermal management of arithmetic units and cache memories, preventing heat from arithmetic units from affecting cache memory operation reliability while maintaining high computing power through the stacked configuration.
Solution Approach 2:
The patent implements different operational states for arithmetic units and cache memories based on local thermal conditions and workload requirements. The operation management circuit selectively activates or deactivates specific arithmetic units or cache memories in response to thermal feedback, creating locally optimized operational quality that prevents heat-induced failures while maximizing computing performance.
2Quantity of substance
If the number of arithmetic units and cache memories is increased through stacking to improve computing power, then memory capacity and computing power are enhanced, but the heat generation from arithmetic units causes cache memory failure
Solution Approach 1:
The patent introduces an operation management circuit as an intermediary between the arithmetic units and cache memories. This circuit receives thermal information and workload data, then mediates the operational state of arithmetic units and cache memories accordingly. The management circuit can deactivate cache memories when thermal conditions are excessive, preventing heat-induced failures while maintaining the ability to scale the number of cache memories for improved memory capacity.
3Productivity
If arithmetic units and cache memories are stacked to increase the number of cores, then computing power is improved, but thermal management becomes more difficult and cache memory reliability decreases
Solution Approach 1:
The patent implements a feedback mechanism where the operation management circuit continuously monitors thermal conditions in the stacked die structure and adjusts the operational state of arithmetic units and cache memories accordingly. This feedback loop enables dynamic thermal management that maintains computing power while preventing thermal issues from compromising cache memory reliability, effectively managing the increased complexity of multi-die thermal management.
Data Source
AI summary
A cache memory equipped arithmetic device includes a first semiconductor die configured to include a plurality of arithmetic circuits, a second semiconductor die stacked over the first semiconductor die, and configured to include a plurality of cache memories, a cache memory of the plurality of cache memories forming a pair with an arithmetic circuit of the plurality of arithmetic circuits, and an operation management circuit configured to manage operation of the first semiconductor die and the second semiconductor die, wherein the arithmetic circuit and the cache memory, which form the pair, at least partially overlap each other in plan view, and wherein the operation management circuit selectively operates one of the arithmetic circuit and the cache memory paired with the arithmetic circuit, based on arithmetic intensity needed for the plurality of arithmetic circuits.