3D Stacked Cache Layout With On-Chip Power Support
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Solution Overview
Problem
Integrated circuits face inefficiencies in power delivery due to high voltage transmission and multiple step-down conversions, leading to increased dynamic power losses and I2R losses in transistors and metal connections.
Innovation Solution
A 3D stacked semiconductor module configuration with separate dies for power support, logic core, and cache memory, where the power support structure is integrated with magnetic materials and regulators to provide efficient voltage conversion and power distribution, allowing for different technology nodes for optimal performance and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power is transmitted at high voltage, then power delivery capability is improved, but dynamic power losses and I2R losses increase
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional stacked architecture, placing power support structures vertically beneath logic cores. This vertical arrangement reduces current path length and resistance, thereby reducing I2R losses while maintaining high power delivery capability.
Solution Approach 2:
The patent introduces on-chip power support structures including voltage regulators and power management circuits as intermediary components between the power source and logic cores. These intermediaries enable localized voltage conversion and distribution, reducing the need for high-voltage transmission across the entire chip and thereby reducing power losses.
2Adaptability or versatility
If multiple step-down voltage conversions are used, then voltage matching is improved, but power efficiency deteriorates
Solution Approach 1:
The patent segments the power distribution system into multiple independent voltage regulator modules, each serving specific logic core regions. This segmentation allows for optimized voltage conversion in each region, reducing the number of sequential step-down conversions needed and thereby improving overall power efficiency while maintaining appropriate voltage levels.
Solution Approach 2:
The patent implements localized power support structures with voltage regulators positioned close to specific logic core regions that require them. This local quality approach enables voltage conversion only where needed, avoiding unnecessary power conversion steps in other regions and improving overall system efficiency.
3Device complexity
If power support and logic cores are integrated on the same die, then device complexity is reduced, but power density and performance are limited
Solution Approach 1:
The patent employs three-dimensional stacking to place power support structures on separate dies vertically beneath logic core dies. This vertical integration maintains electrical connectivity while allowing each die to be optimized for its specific function, achieving high power density without compromising device complexity management.
4Productivity
If advanced memory technologies are used, then performance is improved, but fabrication cost increases
Solution Approach 1:
The patent segments the semiconductor system into separate functional dies, including dedicated memory dies that can be fabricated using optimized processes for each memory technology type. This segmentation allows advanced memory technologies to be implemented in specific dies without requiring the entire chip to use costly advanced fabrication processes, thereby improving performance while controlling costs.
Data Source
AI summary
A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.