3D Stacked Cache Memory Layout for Stable Signal Delay
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Solution Overview
Problem
In semiconductor devices with three-dimensionally stacked Si dies functioning as cache memory, the resistance component due to bonding between Si dies increases with the number of stacked layers, leading to variations in signal delay and reduced computing efficiency, power efficiency, and increased power consumption.
Innovation Solution
A semiconductor device with a novel structure comprising a first element layer with a control portion and a second element layer stacked over the first element layer, where the second element layer includes a set associative type cache memory with n ways and an input/output portion. The n element layers are each equipped with a first transistor having a semiconductor layer with a silicon channel formation region, and through electrodes connect the layers, with metal bumps providing electrical connection between different element layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked Si dies is increased to increase memory capacity, then the memory capacity of the cache memory is increased, but the resistance component between Si dies increases causing variation in signal delay
Solution Approach 1:
The cache memory is divided into multiple independent element layers (first element layer, second element layer, etc.), each containing its own memory cells and control circuits. This segmentation allows each layer to operate independently with localized control, reducing the impact of inter-layer resistance variations on overall signal delay consistency.
Solution Approach 2:
The invention transitions from a planar cache memory structure to a three-dimensional stacked structure with multiple element layers connected via through electrodes. This dimensional change increases memory capacity while managing resistance effects through vertical integration and localized control portions in each layer.
2Quantity of substance
If the number of stacked Si dies is increased to increase memory capacity, then the memory capacity of the cache memory is increased, but power consumption increases and computing efficiency decreases
Solution Approach 1:
Each element layer is equipped with its own control portion that can independently manage memory operations within that layer. This segmentation enables selective activation of only the necessary element layers based on access patterns, reducing overall power consumption while maintaining high memory capacity through the stacked structure.
Solution Approach 2:
Each element layer functions as a self-contained unit with its own control portion that manages local memory operations independently. This self-service capability reduces the need for long-distance signal routing and centralized control, thereby reducing power consumption in the stacked cache memory structure.
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a first element layer including a control portion and a second element layer stacked and provided over the first element layer. The second element layer includes a memory portion that functions as a set associative type cache memory including n ways (n is greater than or equal to 2) and an input/output portion that has a function of inputting/outputting data stored in the memory portion. In the second element layer, n element layers are stacked and provided. The n element layers each include a first transistor. In the first transistor, a semiconductor layer including a channel formation region includes silicon. The n element layers each include the memory portion and the input/output portion that are separately provided. The memory portion provided in any one of the n element layers outputs data corresponding to any one of the n ways to the control portion through the input/output portion provided in any one of the n element layers.